maksyuki a32d9af957 feat: enhance SDRAM Controller and Testbench Functionality ...

- Introduced burst length handling in the SDRAM Verilator model, allowing for more flexible read/write operations.
- Added new SDRAM-related source files to the project structure, including sdram_pkg.sv and sdram_axi4.sv.
- Updated software makefile to include new SDRAM-related C source files for HAL.
- Enhanced C test suite with new tests for SDRAM timing and functionality, ensuring proper integration with the HAL.
- Improved RTL testbench for SDRAM, adding support for burst writes and reads, and verifying data integrity.
- Updated Python test scripts to reflect changes in SDRAM handling and ensure comprehensive coverage of SDRAM functionality.
- Added checks to ensure register offsets between RTL and HAL definitions match, maintaining consistency across the codebase.

2026-08-18 09:06:19 +08:00

..

actions/locked-tools

refactor: refactor RTL paths and update test descriptions

2026-08-13 13:41:52 +08:00

ISSUE_TEMPLATE

chore: add init github action config and commu rules

2025-11-19 11:34:42 +08:00

workflows

feat: enhance SDRAM Controller and Testbench Functionality

2026-08-18 09:06:19 +08:00

CODEOWNERS

refactor: refactor RTL paths and update test descriptions

2026-08-13 13:41:52 +08:00

dependabot.yml

feat: add GUIDE.md for GitHub automation and update references in AGENTS.md and README.md

2026-07-12 09:08:42 +08:00

GUIDE.md

feat: enhance SDRAM Controller and Testbench Functionality

2026-08-18 09:06:19 +08:00