mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
f5b373fd65
- Added timestamp normalization to function in , allowing for optional timestamp input. - Updated command-line interface to accept a timestamp argument for generating deterministic build variant IDs. - Modified in to include a build timestamp in the environment variables. - Introduced a new test suite in to validate the pin-map generator, including tests for duplicate pads and invalid entries. - Added a test for ensuring the regression runner uses a consistent build timestamp. - Created a new SystemVerilog testbench for the APB4 interface bridge to verify correct signal crossing.
90 lines
2.0 KiB
Systemverilog
90 lines
2.0 KiB
Systemverilog
`timescale 1ns / 1ps
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module retrosoc_top (
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input clk_i,
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inout rst_n_i,
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inout ps2_clk_i,
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inout ps2_dat_i,
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output onewire_dat_o,
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inout i2c_scl_io,
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inout i2c_sda_io,
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output pwm_2_o,
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output spisd_sck_o,
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output spisd_nss_o,
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output spisd_mosi_o,
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inout spisd_miso_i,
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output i2s_mclk_o,
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output i2s_sclk_o,
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output i2s_lrck_o,
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output i2s_dacdat_o,
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inout i2s_adcdat_i,
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output psram_sck_o,
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output psram_nss0_o,
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inout psram_dat0_io,
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inout psram_dat1_io,
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inout psram_dat2_io,
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inout psram_dat3_io,
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inout gpio_io30,
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output uart0_tx_o,
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inout uart0_rx_i,
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output xpi_sck_o,
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output xpi_nss0_o,
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inout xpi_dat0_io,
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inout xpi_dat1_io,
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inout xpi_dat2_io,
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inout xpi_dat3_io,
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output sdram_clk_o,
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output sdram_cke_o,
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output sdram_cs_n_o,
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output sdram_ras_n_o,
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output sdram_cas_n_o,
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output sdram_we_n_o,
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output sdram_ba0_o,
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output sdram_ba1_o,
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output sdram_addr0_o,
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output sdram_addr1_o,
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output sdram_addr2_o,
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output sdram_addr3_o,
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output sdram_addr4_o,
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output sdram_addr5_o,
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output sdram_addr6_o,
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output sdram_addr7_o,
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output sdram_addr8_o,
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output sdram_addr9_o,
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output sdram_addr10_o,
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output sdram_addr11_o,
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output sdram_addr12_o,
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output sdram_dqm0_o,
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output sdram_dqm1_o,
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inout sdram_dq0_io,
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inout sdram_dq1_io,
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inout sdram_dq2_io,
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inout sdram_dq3_io,
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inout sdram_dq4_io,
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inout sdram_dq5_io,
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inout sdram_dq6_io,
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inout sdram_dq7_io,
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inout sdram_dq8_io,
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inout sdram_dq9_io,
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inout sdram_dq10_io,
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inout sdram_dq11_io,
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inout sdram_dq12_io,
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inout sdram_dq13_io,
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inout sdram_dq14_io,
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inout sdram_dq15_io
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);
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wire s_sys_clk;
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wire s_aud_clk;
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clk_wiz_0 u_clk_wiz_0 (
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.clk_in1 (clk_i),
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.clk_out1(s_sys_clk),
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.clk_out2(s_aud_clk)
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);
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retrosoc_asic u_retrosoc (
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`include "retrosoc_asic_fpga_mini_bindings.svh"
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);
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endmodule
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