mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
f5b373fd65
- Added timestamp normalization to function in , allowing for optional timestamp input. - Updated command-line interface to accept a timestamp argument for generating deterministic build variant IDs. - Modified in to include a build timestamp in the environment variables. - Introduced a new test suite in to validate the pin-map generator, including tests for duplicate pads and invalid entries. - Added a test for ensuring the regression runner uses a consistent build timestamp. - Created a new SystemVerilog testbench for the APB4 interface bridge to verify correct signal crossing.
29 lines
1.1 KiB
Systemverilog
29 lines
1.1 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module apb4_if_bridge (
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apb4_pure_if.slave apb_pure,
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apb4_if.master timed
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);
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assign timed.paddr = apb_pure.paddr;
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assign timed.pprot = apb_pure.pprot;
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assign timed.psel = apb_pure.psel;
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assign timed.penable = apb_pure.penable;
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assign timed.pwrite = apb_pure.pwrite;
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assign timed.pwdata = apb_pure.pwdata;
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assign timed.pstrb = apb_pure.pstrb;
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assign apb_pure.pready = timed.pready;
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assign apb_pure.prdata = timed.prdata;
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assign apb_pure.pslverr = timed.pslverr;
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endmodule
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