mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
f5b373fd65
- Added timestamp normalization to function in , allowing for optional timestamp input. - Updated command-line interface to accept a timestamp argument for generating deterministic build variant IDs. - Modified in to include a build timestamp in the environment variables. - Introduced a new test suite in to validate the pin-map generator, including tests for duplicate pads and invalid entries. - Added a test for ensuring the regression runner uses a consistent build timestamp. - Created a new SystemVerilog testbench for the APB4 interface bridge to verify correct signal crossing.
92 lines
2.2 KiB
Systemverilog
92 lines
2.2 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "gpio_define.svh"
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`include "mdd_config.svh"
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module retrosoc_asic (
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`include "retrosoc_asic_ports.svh"
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);
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logic s_ext_clk;
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logic s_aud_clk;
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logic s_sys_clkdiv4;
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`ifdef HAVE_PLL
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logic s_xtal_io;
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`endif
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logic s_sys_clk;
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logic s_ext_rst_n;
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logic s_sys_rst_n;
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logic s_aud_rst_n;
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`ifdef CORE_MDD
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logic [`USER_CORESEL_WIDTH-1:0] s_core_sel;
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`endif
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`ifdef IP_MDD
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gpio_if #(`USER_GPIO_NUM) u_user_gpio_if ();
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`endif
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`ifdef HAVE_SRAM_IF
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ram_if u_ram_if ();
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`endif
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gpio_if u_gpio_if ();
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uart_if u_uart0_if ();
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xpi_if u_xpi_if ();
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sdram_if u_sdram_if ();
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pll_ctrl_if u_pll_ctrl_if ();
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`include "retrosoc_asic_pad_bindings.svh"
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rcu u_rcu (
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.ext_clk_i (s_ext_clk),
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.aud_clk_i (s_aud_clk),
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.ext_rst_n_i (s_ext_rst_n),
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`ifdef HAVE_PLL
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.xtal_clk_i (s_xtal_io),
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`endif
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.pll_ctrl (u_pll_ctrl_if),
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.sys_clk_o (s_sys_clk),
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.sys_rst_n_o (s_sys_rst_n),
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.aud_rst_n_o (s_aud_rst_n),
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.sys_clkdiv4_o(s_sys_clkdiv4)
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);
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`ifdef HAVE_SRAM_IF
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onchip_ram u_onchip_ram (
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.clk_i(s_sys_clk),
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.ram (u_ram_if)
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);
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`endif
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retrosoc u_retrosoc (
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.clk_i (s_sys_clk),
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.rst_n_i (s_sys_rst_n),
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.clk_aud_i (s_aud_clk),
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.rst_aud_n_i(s_aud_rst_n),
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.clkdiv4_i (s_sys_clkdiv4),
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.pll_ctrl (u_pll_ctrl_if),
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`ifdef CORE_MDD
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.core_sel_i (s_core_sel),
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`endif
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`ifdef IP_MDD
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.user_gpio (u_user_gpio_if),
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`endif
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`ifdef HAVE_SRAM_IF
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.ram (u_ram_if),
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`endif
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.gpio (u_gpio_if),
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.uart0 (u_uart0_if),
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.xpi (u_xpi_if),
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.sdram (u_sdram_if)
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);
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endmodule
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