mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
f6190f91e6
Add optional Tiny NSS1 PSRAM initialization, identity and geometry checks, mapped CPU/DMA workload coverage, and retained pin-level device verification. Harden shared XPI byte lanes, burst boundaries, response completion and timeout behavior while preserving NOR/SRAM-only boot and Mini compatibility.\n\nValidation: focused P8/XPI tests, ICS55 and IHP130 Verilator P8 replays, Tiny netlist boot, synthesis and observational STA completed. Full long-running Icarus firmware remains deferred to final Tiny qualification.
181 lines
7.8 KiB
C
181 lines
7.8 KiB
C
#include <retrosoc/arch/riscv/system_base.h>
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#include <retrosoc/hal/dma.h>
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#include <retrosoc/hal/gpio.h>
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#include <retrosoc/hal/rcu.h>
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#include <retrosoc/hal/sysctrl.h>
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#include <retrosoc/hal/uart.h>
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#include <retrosoc/hal/xpi_psram.h>
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#include <retrosoc/lib/printf.h>
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#define RS_P8_WORDS UINT32_C(256)
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#define RS_P8_ADDRESS UINT32_C(0x54000c00)
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static _Alignas(64) uint32_t rs_p8_source[RS_P8_WORDS];
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static _Alignas(64) uint32_t rs_p8_readback[RS_P8_WORDS];
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static volatile uint32_t rs_p8_cpu_progress;
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typedef struct {
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uint32_t sys_hz, mem_hz;
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uint32_t isolated_cycles, contended_cycles, progress;
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} rs_p8_measurement_t;
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static rs_p8_measurement_t rs_p8_results[3];
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static bool rs_p8_dma(rs_dma_session_t *session, uintptr_t source, uintptr_t destination,
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bool contend, uint32_t *cycles) {
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const rs_dma_config_t config = {.kind = RS_DMA_KIND_MM_TO_MM,
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.request = RS_DMA_REQUEST_SOFTWARE,
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.source = source,
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.destination = destination,
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.byte_count = sizeof(rs_p8_source),
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.width = RS_DMA_WIDTH_32,
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.source_increment = true,
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.destination_increment = true,
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.burst_beats = RS_XPI_PSRAM_BURST_BEATS};
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rs_dma_status_t state = {0};
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rs_timeout_t timeout = RS_TIMEOUT_DEFAULT;
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uint64_t start;
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if (rs_dma_session_configure(session, &config) != RS_OK ||
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rs_sysctrl_set_perf_control(true, true, false) != RS_OK) {
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return false;
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}
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__FENCE(rw, rw);
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start = __get_rv_cycle();
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if (rs_dma_session_start(session) != RS_OK) {
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return false;
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}
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do {
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if (contend) {
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/* Defined competing SRAM work, with no race on the DMA buffers. */
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rs_p8_cpu_progress++;
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}
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if (timeout-- == 0U || rs_dma_get_status(session->channel, &state) != RS_OK) {
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return false;
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}
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} while (state.busy);
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*cycles = (uint32_t)(__get_rv_cycle() - start);
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__FENCE(rw, rw);
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if (rs_sysctrl_set_perf_control(false, false, false) != RS_OK) {
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return false;
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}
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return state.done && !state.error && !state.aborted &&
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state.bytes_done == sizeof(rs_p8_source) && state.remaining == 0U;
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}
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static bool rs_p8_profile(rs_tiny_rcu_profile_t profile, rs_p8_measurement_t *measurement) {
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rs_tiny_rcu_snapshot_t clocks;
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rs_xpi_psram_t device;
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rs_dma_session_t session;
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volatile uint32_t *const memory = (volatile uint32_t *)(uintptr_t)RS_P8_ADDRESS;
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volatile uint32_t *const first = (volatile uint32_t *)(uintptr_t)RS_XPI_PSRAM_BASE;
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volatile uint32_t *const last = (volatile uint32_t *)(uintptr_t)UINT32_C(0x547ffffc);
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bool pass = true;
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uint32_t unused_cycles;
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if (rs_tiny_rcu_request_profile(profile, RS_TIMEOUT_DEFAULT) != RS_OK ||
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rs_tiny_rcu_get_snapshot(&clocks) != RS_OK ||
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rs_xpi_psram_initialize(clocks.mem_hz, RS_TIMEOUT_DEFAULT, &device) != RS_OK ||
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rs_xpi_psram_validate_dma(&device, RS_P8_ADDRESS, sizeof(rs_p8_source), 4U) != RS_OK) {
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return false;
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}
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measurement->sys_hz = clocks.sys_hz;
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measurement->mem_hz = clocks.mem_hz;
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*first = 0U;
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*(volatile uint8_t *)(uintptr_t)(RS_XPI_PSRAM_BASE + 1U) = UINT8_C(0xa5);
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*(volatile uint16_t *)(uintptr_t)(RS_XPI_PSRAM_BASE + 2U) = UINT16_C(0xbeef);
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*last = UINT32_C(0x2468ace0);
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if (*first != UINT32_C(0xbeefa500) || *last != UINT32_C(0x2468ace0)) {
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return false;
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}
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if (rs_dma_session_acquire(&session, RS_DMA_CHANNEL_BULK) != RS_OK) {
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return false;
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}
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for (uint32_t round = 0U; round < 2U && pass; round++) {
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for (uint32_t i = 0U; i < RS_P8_WORDS; i++) {
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rs_p8_source[i] = UINT32_C(0x13579bdf) ^ (i * UINT32_C(0x01010101)) ^ round;
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rs_p8_readback[i] = 0U;
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}
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*(volatile uint32_t *)(uintptr_t)(RS_P8_ADDRESS - 4U) = UINT32_C(0x55aa55aa);
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memory[RS_P8_WORDS] = UINT32_C(0xaa55aa55);
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rs_p8_cpu_progress = 0U;
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pass =
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rs_p8_dma(&session, (uintptr_t)rs_p8_source, RS_P8_ADDRESS, round != 0U,
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round == 0U ? &measurement->isolated_cycles : &measurement->contended_cycles);
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measurement->progress = rs_p8_cpu_progress;
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for (uint32_t i = 0U; i < RS_P8_WORDS && pass; i++) {
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pass = memory[i] == rs_p8_source[i];
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}
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if (pass) {
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pass = rs_p8_dma(&session, RS_P8_ADDRESS, (uintptr_t)rs_p8_readback, false,
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&unused_cycles);
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}
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for (uint32_t i = 0U; i < RS_P8_WORDS && pass; i++) {
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pass = rs_p8_readback[i] == rs_p8_source[i];
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}
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pass = pass &&
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(*(volatile uint32_t *)(uintptr_t)(RS_P8_ADDRESS - 4U) == UINT32_C(0x55aa55aa)) &&
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(memory[RS_P8_WORDS] == UINT32_C(0xaa55aa55));
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}
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if (!pass && rs_dma_abort_wait(session.channel, RS_TIMEOUT_DEFAULT) != RS_OK) {
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return false; /* Static buffers remain owned; terminal failure follows. */
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}
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return rs_dma_session_release(&session) == RS_OK && pass && measurement->progress != 0U;
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}
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int main(void) {
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const rs_gpio_config_t pin = {.mode = RS_GPIO_MODE_ALT0,
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.pull = RS_GPIO_PULL_NONE,
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.trigger = RS_GPIO_TRIGGER_NONE,
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.output_high = true};
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rs_tiny_rcu_snapshot_t clocks;
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rs_xpi_psram_t device;
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rs_status_t status;
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const uint32_t nor_word = *(volatile const uint32_t *)(uintptr_t)UINT32_C(0x50000000);
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uint32_t count = 0U;
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uint8_t code = 0U;
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__disable_irq();
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if (rs_gpio_configure(29U, &pin) != RS_OK || rs_tiny_rcu_get_snapshot(&clocks) != RS_OK) {
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code = 1U;
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} else {
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status = rs_xpi_psram_initialize(clocks.mem_hz, RS_TIMEOUT_DEFAULT, &device);
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if (status == RS_ENOTSUP && !device.initialized && device.capacity_bytes == 0U) {
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(void)rs_uart_init(24000000U, 921600U);
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printf("P8_ABSENT bounded optional-device rejection\n");
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code =
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(*(volatile const uint32_t *)(uintptr_t)UINT32_C(0x50000000) == nor_word) ? 0U : 2U;
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} else if (status != RS_OK) {
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code = 3U;
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} else {
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if (!rs_p8_profile(RS_TINY_RCU_PROFILE_SAFE24, &rs_p8_results[count++])) {
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code = 4U;
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}
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if (code == 0U && (clocks.capability & 12U) == 12U) {
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if (!rs_p8_profile(RS_TINY_RCU_PROFILE_PLL192, &rs_p8_results[count++]) ||
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!rs_p8_profile(RS_TINY_RCU_PROFILE_PLL240, &rs_p8_results[count++])) {
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code = 5U;
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}
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} else if (code == 0U && clocks.xin_hz != 24000000U) {
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if (!rs_p8_profile(RS_TINY_RCU_PROFILE_XIN, &rs_p8_results[count++])) {
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code = 6U;
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}
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}
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if (code == 0U && rs_tiny_rcu_request_profile(RS_TINY_RCU_PROFILE_SAFE24,
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RS_TIMEOUT_DEFAULT) != RS_OK) {
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code = 7U;
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}
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if (code == 0U &&
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*(volatile const uint32_t *)(uintptr_t)UINT32_C(0x50000000) != nor_word) {
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code = 8U;
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}
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}
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}
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(void)rs_uart_init(24000000U, 921600U);
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for (uint32_t i = 0U; i < count; i++) {
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printf("P8_TRANSPORT sys_hz=%u mem_hz=%u bytes=1024 burst=4 isolated_cycles=%u "
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"contended_cycles=%u progress=%u\n",
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rs_p8_results[i].sys_hz, rs_p8_results[i].mem_hz, rs_p8_results[i].isolated_cycles,
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rs_p8_results[i].contended_cycles, rs_p8_results[i].progress);
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}
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printf("P8_RESULT code=%u profiles=%u\n", code, count);
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rs_sysctrl_write_test_status(code == 0U, code);
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for (;;) {
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}
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}
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