mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-05 06:32:37 +00:00
maksyuki
4e6ab1a6fb
- Introduced for formal verification of fault handling in the Tiny R2 P5 architecture. - Added to test target reset isolation and ensure proper handling of reset signals across multiple targets. - Created to validate system-level interactions, including CPU and DMA progress during resets. - Enhanced to include fault counting and master tracking for concurrent fault events. - Developed to automate testing of concurrency, fault accounting, and retained-image acceptance. - Updated Python test suite to validate new configurations and ensure proper integration with Tiny R2 P5 architecture.
84 lines
3.9 KiB
JSON
84 lines
3.9 KiB
JSON
{
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"schema_version": 1,
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"targets": [
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{
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"name": "tiny-r2-p5",
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"paths": ["rtl/tiny/top"],
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"status": "prototype",
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"baseline_revision": "3131762b35e0ebfcd196395f955e7c1005bd18e7",
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"configuration_digest": null,
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"configuration_profiles": ["configs/ci/ics55-tiny.mk", "configs/ci/ihp130-tiny.mk"],
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"required_evidence": [],
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"synthesis_intent": {
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"registers": "Common registers and bounded response spill registers per external target",
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"reset": "accepted CPU work drains before hart reset; system reset invalidates all sessions",
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"clock_enable": "all fabric, APB, CPU and SRAM logic remains on direct SAFE24 SYS",
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"memory": "unchanged 32 SRAM macros; no global SRAM transaction lock",
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"pipeline": "one combined transaction per target, CPU one combined, DMA/SDIO one per direction"
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},
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"waivers": []
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},
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{
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"name": "tiny-r2-p4",
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"paths": ["rtl/tiny/top"],
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"status": "prototype",
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"baseline_revision": "4db27524a6282ca40d76b935415b89f043d6ea83",
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"configuration_digest": null,
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"configuration_profiles": ["configs/ci/ics55-tiny.mk", "configs/ci/ihp130-tiny.mk"],
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"required_evidence": [],
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"synthesis_intent": {
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"registers": "Common registers; independent I/D request state and per-group responses",
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"reset": "five-edge release; hart halt/drain leaves SRAM and unrelated DMA active",
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"clock_enable": "CPU and all 32 main-SRAM macros use direct SAFE24 SYS",
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"memory": "four groups of eight tc_sram_1024x32 macros; no payload reset or extra SRAM",
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"pipeline": "AHB capture, macro issue, registered response; uncontended completion within three cycles"
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},
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"waivers": []
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},
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{
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"name": "owned-rtl",
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"paths": [
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"rtl/ip",
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"rtl/mini/top",
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"rtl/tiny/top"
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],
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"status": "prototype",
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"baseline_revision": null,
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"configuration_digest": null,
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"configuration_profiles": [
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"all"
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],
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"required_evidence": [],
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"synthesis_intent": {
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"registers": "ClusterIP Common register primitives are the default storage boundary",
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"reset": "rst_n_i is active-low; reset and enable precedence is documented per module",
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"clock_enable": "register enables are explicit and visible to synthesis",
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"memory": "infer or instantiate memories according to the selected PDK profile",
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"pipeline": "critical pipeline boundaries are documented by the owning IP"
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},
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"waivers": []
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},
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{
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"name": "crypto-p1",
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"paths": ["rtl/ip/security"],
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"status": "prototype",
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"baseline_revision": "92830d963da2f1e39bb219c0d377bc4889c07755",
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"configuration_digest": null,
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"configuration_profiles": ["configs/ci/ihp130.mk"],
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"required_evidence": [
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{"kind": "simulation", "path": "tests/rtl/crypto_v2_tb.sv"},
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{"kind": "formal", "path": "rtl/mini/formal/crypto_control_formal.sv"},
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{"kind": "synthesis", "path": "scripts/crypto_p1.py"}
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],
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"synthesis_intent": {
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"registers": "Common scalar/control registers; only the active AES 128-bit and SHA eight-word working state remain wide. RSA operands are SRAM limbs.",
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"reset": "Asynchronous validity reset followed by parallel write-zero/readback of banks 2-5 and explicit FIFO payload erasure; reset never initializes a SRAM array directly.",
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"clock_enable": "PCLK only; no gated clock. Tagged fixed-latency SRAM retirements control engine progress.",
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"memory": "Exactly six tc_sram_1024x32 banks on IHP130; explicit macro-disabled synchronous fallback; only 8x37, 8x37 and 16x37 Common FIFOs may infer production storage.",
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"pipeline": "One access per bank/cycle. AES owns banks 0/2, SHA owns 1/3, RSA owns 4/5; APB accesses idle owners and maintenance takes priority. P2 physical qualification remains pending."
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},
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"waivers": []
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}
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]
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}
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