maksyuki
bfdc3ffaf6
- Introduced the PPALite extension, approved on 2026-10-05, detailing its features such as camera-inline Y extraction, RGB565 ordering, and fixed pixel/line sampling. - Updated the tiny-soc-verification and tiny-soc documentation to reflect the new PPALite extension, including its integration with existing DVP and DMA channels. - Added comprehensive evidence tables for PPALite phases (PPALITE-P0 to P5) outlining required evidence and current statuses. - Clarified the relationship between PPALite and existing SPI/PIO extensions, emphasizing that earlier results cannot qualify newly added PPALite logic. - Enhanced the README files in the RTL directory to specify PPALite's role and requirements in the context of Tiny SoC development.
4.1 KiB
AXI4-Stream Peripheral Data Paths
The Mini SoC uses 32-bit AXI4-Stream links for high-rate peripheral data that does not need an address on every word. APB4 remains the register configuration plane. The active stream endpoints are DMA to I2S TX, I2S RX to DMA, and DVP RX to DMA. UART, I2C, and WS2812 retain their existing APB4 FIFO data registers.
The separately frozen Tiny PIO-lite extension adds a planned central-DMA TX/RX pair at requests 14/15 through DMA V2.1. Its PCLK 32-bit streams use full-word keep/strobe, one selected SM per direction, exclusive channel-bound sessions and explicit abort/drain/isolation. It is not implemented or enabled on Mini by this document. The historical I2S/DVP rules below do not substitute for PIO-lite's packing, ownership or reset contract; the existing Crypto streams retain their own framing rules.
The separately frozen Tiny SPI master uses DMA V2.2 paced fixed MMIO requests16/17, not new AXI4-Stream ports. Its source-qualified admission, credits, R/B drain and exact serial-frame completion must not be substituted with stream VALID/TLAST rules. PIO14/15 and the stream-direction count remain unchanged by that SPI extension.
The separately frozen Tiny PPALite route inserts processing after DVP's existing CDC FIFO and before the same request11/DMA2 endpoint. RAW preserves all source words/sidebands; PROCESS accepts legal halfword line tails, selects/converts pixels and zero-pads each output row to full-word KEEP/STRB. No stream endpoint or request is added. SOF marks the first emitted word, TLAST remains EOL, and exact padded byte count plus source/processor/ DMA response checks determine validity. Route changes and failure isolation must obey the full linked contract; FRAME_DONE/PIPE_DONE is not memory completion.
Interface Contract
All three links use DATA_WIDTH=32, one-bit ID, destination, and user fields,
and the system clock/reset. I2S uses TKEEP/TSTRB=4'hF; DVP can mark an
odd-pixel line's final partial word. The DMA MVP accepts only full
TKEEP=4'hF words and reports a stream error for a partial DVP beat. DMA holds
TDATA, TKEEP,
TSTRB, and TLAST stable while TVALID is high and TREADY is low. A word
is consumed only on a TVALID && TREADY clock edge.
DMA asserts TLAST on the final programmed I2S TX word. I2S RX and DVP do not
currently provide a packet boundary to DMA, so DMA terminates their transfers
using its programmed XFERLEN; incoming TLAST is informational and ignored.
IDs and destinations are zero. I2S user sidebands are zero; DVP uses
TUSER[0] for SOF as defined by its current source contract.
Processed PPALite output relocates that marker to its first retained output
word without redefining TLAST as end-of-frame.
Configuration and PIO Fallback
I2S register offset 0x00C is STREAM_CTRL: bit 0 selects AXI4-Stream as the
TX FIFO producer and bit 1 selects AXI4-Stream as the RX FIFO consumer. A clear
bit preserves the existing TXDATA or RXDATA PIO behavior. Software must not
change a stream-select bit while that direction is active. TXDATA is 0x01C
and RXDATA is 0x020.
DVP register offset 0x0C is STREAM_CTRL: bit 0 selects AXI4-Stream as the
RX FIFO consumer. When clear, reads of RXDATA retain the existing pop
behavior. When set, RXDATA reads do not pop the FIFO.
The DMA direct-mode request selectors I2S_TX, I2S_RX, and DVP_RX use the
I2S TX/RX and DVP RX stream links. The source address is unused for stream RX
and the destination address is unused for I2S TX. The channel-aware SDK uses
zero for these unused fields rather than inventing a fake MMIO address. DMA
writes received stream words to AXI4 memory and reads I2S TX words from AXI4
memory.
Verification Boundary
The DMA directed test covers native-AXI4 stream TX backpressure, two-word stream RX to memory, exact transfer length, and bus errors. The I2S and DVP FIFO tests continue to cover PIO mode. Physical audio and camera clock-domain behavior remains controller-specific and must be verified with board-level timing and device models.