maksyuki
8e257d8043
- Revised WS2812 documentation to clarify the shared block and integration details for Mini and Tiny targets. - Enhanced PLL Dynamic Clock Control document to specify differences between Mini and Tiny RCU implementations. - Updated SoC Family Positioning to reflect changes in the Gen1 product/package target, including shared IP and DMA details. - Adjusted Tiny MCU Integration README to include new features and requirements for the 2026-09-30 P6 target, emphasizing the shared peripherals and clock specifications.
2.7 KiB
PLL Dynamic Clock Control
This document describes the Mini LP/HP RCU and its product-specific software
backend. The Tiny Gen1 contract owns a different RCU bank,
driver backend, clock/reset tree and fault-recovery policy in the same SYSCTRL
window. Shared peripheral drivers consume platform clock context; they must
not assume that these Mini register offsets/control semantics apply to Tiny.
Both products retain the existing HAVE_PLL selector and may reuse qualified
technology/Common primitives without sharing product RCU implementation.
The system powers up on the extclk_i_pad external safe clock. After software
submits a PLL frequency request through SYSCTRL, the RCU switches to the safe
source, configures the PLL, waits for lock, and switches back in the external
reference-clock domain. PLL lock transitions do not reset the system. A failed
configuration leaves the system on the safe clock.
Registers
| Offset | Name | Access | Description |
|---|---|---|---|
0x08 |
PLL_CFG |
RW | HP_PSTATE[2:0]: 72, 96, 120, 144, 168, 192, 216, or 240 MHz. |
0x0c |
PLL_CMD |
WO | bit 0 is APPLY; bit 1 is CLEAR_ERROR. |
0x1c |
PLL_STATUS |
RO | Active profile, validity, busy state, error and cause, safe-clock source, lock state, and capability. |
Applications use rs_clock_set_frequency() and rs_clock_get_status() from
<retrosoc/hal/clock.h>; PDK-specific PLL divider settings are not exposed.
Software Flow
- Run the transition routine from SRAM, disable interrupts, and quiesce DMA, serial transfers, and other frequency-sensitive transactions.
- Call
rs_clock_set_frequency()and wait with a bounded timeout. The programmedCLK_TIMEOUTis also the AON quiesce and PLL-lock budget. - On success, reprogram UART, SPI, I2C, timer, and other divider-dependent peripherals for the new frequency before restoring normal operation.
RS_ENOTSUPmeans the current PDK has no integrated dynamic PLL or glitch-free clock-switch backend. The system remains on the external safe clock.
PDK_BEHAV provides all eight dynamic frequencies and lock behavior. A real PDK
must integrate a characterized PLL macro, lock timing, and glitch-free clock
switch before setting capability to 1. The ICS55 hard wrapper advertises only
the qualified selector-0 configuration; requests for other selectors fail safe.
AON Gray-counter monitors track EXT72, HP root, PCLK, and the stable memory
root without sampling their pulses directly at 24 MHz. A stopped clock sets a
sticky clock fault. CLK_GATE[0] drives the HP-core leaf ICG; the AXI64 fabric
and memory root remain active for management recovery and DMA. Technology
timing, scan force-on, and analogue PLL qualification remain physical gates.