mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
fb3621e6b8
- Introduced for handling QSPI flash memory operations, including command and address handling. - Added to interface with the C++ flash memory implementation, allowing for read operations via DPI-C. - Created for the flash memory implementation, supporting initialization, reading, and memory copying. - Updated to integrate the new QSPI Flash module and connect it with the existing system. - Refactored file paths in various filelists and scripts to accommodate the new directory structure under . - Enhanced the Python scripts for generating memory maps and preparing the environment for the new structure. - Adjusted test scripts to reflect changes in the directory structure and ensure compatibility with the new modules.
217 lines
7.5 KiB
Systemverilog
217 lines
7.5 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "mmap_define.svh"
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module nmi2apb (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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nmi_if.slave nmi,
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`ifdef IP_MDD
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apb4_pure_if.master user_ip,
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`endif
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apb4_pure_if.master archinfo,
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apb4_pure_if.master rng,
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apb4_pure_if.master uart,
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apb4_pure_if.master pwm,
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apb4_pure_if.master ps2,
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apb4_pure_if.master rtc,
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apb4_pure_if.master wdg,
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apb4_pure_if.master crc,
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apb4_pure_if.master tmr
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// verilog_format: on
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);
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localparam FSM_IDLE = 2'd0;
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localparam FSM_SETP = 2'd1;
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localparam FSM_ENAB = 2'd2;
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logic [31:0] s_rd_data;
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logic s_xfer_valid, s_xfer_ready;
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logic s_mem_valid_re;
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logic [1:0] s_fsm_d, s_fsm_q;
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// Registered slave-select one-hot for response mux
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`ifdef IP_MDD
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localparam NSLV = 10;
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`else
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localparam NSLV = 9;
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`endif
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logic [NSLV-1:0] s_psel_comb, s_psel_d, s_psel_q;
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// verilog_format: off
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assign archinfo.paddr = nmi.addr;
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assign rng.paddr = nmi.addr;
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assign uart.paddr = nmi.addr;
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assign pwm.paddr = nmi.addr;
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assign ps2.paddr = nmi.addr;
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assign rtc.paddr = nmi.addr;
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assign wdg.paddr = nmi.addr;
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assign crc.paddr = nmi.addr;
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assign tmr.paddr = nmi.addr;
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assign archinfo.pprot = '0;
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assign rng.pprot = '0;
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assign uart.pprot = '0;
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assign pwm.pprot = '0;
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assign ps2.pprot = '0;
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assign rtc.pprot = '0;
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assign wdg.pprot = '0;
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assign crc.pprot = '0;
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assign tmr.pprot = '0;
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assign archinfo.psel = s_xfer_valid && `SOC_ADDR_IS_APB_ARCHINFO(nmi.addr);
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assign rng.psel = s_xfer_valid && `SOC_ADDR_IS_APB_RNG(nmi.addr);
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assign uart.psel = s_xfer_valid && `SOC_ADDR_IS_APB_UART1(nmi.addr);
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assign pwm.psel = s_xfer_valid && `SOC_ADDR_IS_APB_PWM(nmi.addr);
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assign ps2.psel = s_xfer_valid && `SOC_ADDR_IS_APB_PS2(nmi.addr);
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assign rtc.psel = s_xfer_valid && `SOC_ADDR_IS_APB_RTC(nmi.addr);
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assign wdg.psel = s_xfer_valid && `SOC_ADDR_IS_APB_WDG(nmi.addr);
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assign crc.psel = s_xfer_valid && `SOC_ADDR_IS_APB_CRC(nmi.addr);
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assign tmr.psel = s_xfer_valid && `SOC_ADDR_IS_APB_TMR(nmi.addr);
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assign archinfo.penable = s_fsm_q == FSM_ENAB;
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assign rng.penable = s_fsm_q == FSM_ENAB;
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assign uart.penable = s_fsm_q == FSM_ENAB;
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assign pwm.penable = s_fsm_q == FSM_ENAB;
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assign ps2.penable = s_fsm_q == FSM_ENAB;
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assign rtc.penable = s_fsm_q == FSM_ENAB;
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assign wdg.penable = s_fsm_q == FSM_ENAB;
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assign crc.penable = s_fsm_q == FSM_ENAB;
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assign tmr.penable = s_fsm_q == FSM_ENAB;
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assign archinfo.pwrite = |nmi.wstrb;
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assign rng.pwrite = |nmi.wstrb;
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assign uart.pwrite = |nmi.wstrb;
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assign pwm.pwrite = |nmi.wstrb;
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assign ps2.pwrite = |nmi.wstrb;
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assign rtc.pwrite = |nmi.wstrb;
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assign wdg.pwrite = |nmi.wstrb;
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assign crc.pwrite = |nmi.wstrb;
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assign tmr.pwrite = |nmi.wstrb;
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assign archinfo.pwdata = nmi.wdata;
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assign rng.pwdata = nmi.wdata;
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assign uart.pwdata = nmi.wdata;
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assign pwm.pwdata = nmi.wdata;
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assign ps2.pwdata = nmi.wdata;
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assign rtc.pwdata = nmi.wdata;
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assign wdg.pwdata = nmi.wdata;
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assign crc.pwdata = nmi.wdata;
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assign tmr.pwdata = nmi.wdata;
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assign archinfo.pstrb = nmi.wstrb;
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assign rng.pstrb = nmi.wstrb;
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assign uart.pstrb = nmi.wstrb;
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assign pwm.pstrb = nmi.wstrb;
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assign ps2.pstrb = nmi.wstrb;
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assign rtc.pstrb = nmi.wstrb;
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assign wdg.pstrb = nmi.wstrb;
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assign crc.pstrb = nmi.wstrb;
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assign tmr.pstrb = nmi.wstrb;
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`ifdef IP_MDD
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assign user_ip.paddr = nmi.addr;
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assign user_ip.pprot = '0;
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assign user_ip.psel = s_xfer_valid && `SOC_ADDR_IS_APB_USER_IP(nmi.addr);
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assign user_ip.penable = s_fsm_q == FSM_ENAB;
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assign user_ip.pwrite = |nmi.wstrb;
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assign user_ip.pwdata = nmi.wdata;
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assign user_ip.pstrb = nmi.wstrb;
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`endif
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// verilog_format: on
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edge_det_sync_re #(1) u_mem_valid_edge_det_sync_re (
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clk_i,
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rst_n_i,
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nmi.valid,
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s_mem_valid_re
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);
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assign s_xfer_valid = ((s_fsm_q == FSM_IDLE) && s_mem_valid_re) ||
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(s_fsm_q == FSM_SETP) || (s_fsm_q == FSM_ENAB);
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always_comb begin
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s_fsm_d = s_fsm_q;
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unique case (s_fsm_q)
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FSM_IDLE: if (s_mem_valid_re) s_fsm_d = FSM_SETP;
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FSM_SETP: s_fsm_d = FSM_ENAB;
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FSM_ENAB: if (s_xfer_ready) s_fsm_d = FSM_IDLE;
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default: s_fsm_d = s_fsm_q;
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endcase
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end
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dffr #(2) u_fsm_dffr (
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clk_i,
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rst_n_i,
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s_fsm_d,
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s_fsm_q
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);
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assign nmi.ready = nmi.valid && (s_fsm_q == FSM_ENAB) && s_xfer_ready;
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assign nmi.rdata = {32{nmi.ready}} & s_rd_data;
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// Capture slave-select one-hot at FSM_SETP for cleaner response mux
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// verilog_format: off
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assign s_psel_comb[0] = `SOC_ADDR_IS_APB_ARCHINFO(nmi.addr);
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assign s_psel_comb[1] = `SOC_ADDR_IS_APB_RNG(nmi.addr);
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assign s_psel_comb[2] = `SOC_ADDR_IS_APB_UART1(nmi.addr);
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assign s_psel_comb[3] = `SOC_ADDR_IS_APB_PWM(nmi.addr);
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assign s_psel_comb[4] = `SOC_ADDR_IS_APB_PS2(nmi.addr);
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assign s_psel_comb[5] = `SOC_ADDR_IS_APB_RTC(nmi.addr);
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assign s_psel_comb[6] = `SOC_ADDR_IS_APB_WDG(nmi.addr);
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assign s_psel_comb[7] = `SOC_ADDR_IS_APB_CRC(nmi.addr);
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assign s_psel_comb[8] = `SOC_ADDR_IS_APB_TMR(nmi.addr);
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`ifdef IP_MDD
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assign s_psel_comb[9] = `SOC_ADDR_IS_APB_USER_IP(nmi.addr);
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`endif
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assign s_psel_d = (s_fsm_q == FSM_IDLE && s_mem_valid_re) ? s_psel_comb : s_psel_q;
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// verilog_format: on
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dffr #(NSLV) u_psel_dffr (
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clk_i,
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rst_n_i,
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s_psel_d,
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s_psel_q
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);
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// Response mux using registered slave-select (cleaner timing)
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// verilog_format: off
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assign s_rd_data = ({32{s_psel_q[0]}} & archinfo.prdata) |
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({32{s_psel_q[1]}} & rng.prdata) |
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({32{s_psel_q[2]}} & uart.prdata) |
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({32{s_psel_q[3]}} & pwm.prdata) |
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({32{s_psel_q[4]}} & ps2.prdata) |
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({32{s_psel_q[5]}} & rtc.prdata) |
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({32{s_psel_q[6]}} & wdg.prdata) |
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({32{s_psel_q[7]}} & crc.prdata) |
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`ifdef IP_MDD
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({32{s_psel_q[9]}} & user_ip.prdata) |
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`endif
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({32{s_psel_q[8]}} & tmr.prdata);
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assign s_xfer_ready = (s_psel_q[0] & archinfo.pready) |
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(s_psel_q[1] & rng.pready) |
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(s_psel_q[2] & uart.pready) |
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(s_psel_q[3] & pwm.pready) |
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(s_psel_q[4] & ps2.pready) |
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(s_psel_q[5] & rtc.pready) |
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(s_psel_q[6] & wdg.pready) |
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(s_psel_q[7] & crc.pready) |
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`ifdef IP_MDD
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(s_psel_q[9] & user_ip.pready) |
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`endif
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(s_psel_q[8] & tmr.pready);
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// verilog_format: on
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endmodule
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