mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fb3621e6b8
- Introduced for handling QSPI flash memory operations, including command and address handling. - Added to interface with the C++ flash memory implementation, allowing for read operations via DPI-C. - Created for the flash memory implementation, supporting initialization, reading, and memory copying. - Updated to integrate the new QSPI Flash module and connect it with the existing system. - Refactored file paths in various filelists and scripts to accommodate the new directory structure under . - Enhanced the Python scripts for generating memory maps and preparing the environment for the new structure. - Adjusted test scripts to reflect changes in the directory structure and ensure compatibility with the new modules.
314 lines
9.5 KiB
Systemverilog
314 lines
9.5 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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//
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// NOTE: for supporting cross page xfer, the max freq of 'sclk' is 84MHz
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// when 'sclk' is 144MHz(max, ~6.94ns), according to TRM:
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//
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// tCLK(min: 6.94ns) is meet, dont have 8'h03 rd oper(min: 30.3ns)
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//
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// tCH/tCL(min:0.45%, max: 0.55%) tCLK is meet
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//
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// tKHKL(max: 1.5ns) is meet
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//
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// tCPH(min: 50ns) -> 50 / 6.94 = ~7.2 so wait cycles need to >= ceil(7.2) = 8,
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// so 'r_cfg_wait' = 8 * 2 >= 16 in default, reset value is '18'
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// for lower freq, can modify this value for performance tuning
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//
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// tCEM(max: 8us) is enough long for just 32bits xfer:
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// QPI mode: (32(cmd+addr) + 32(data)) / 4 = 16 cycles + 6 wait cycles = 22 cycles
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// for min sclk 12MHz, ~83ns * 22 = 1826ns = 1.826us
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//
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// tCSP(min: 2.5ns) is meet
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// sclk keeps 6.94 / 2 = 3.47ns low at least after ce activing
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//
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// tCHD(min: 20ns) > tACLK + tCLK
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// sclk keep 6.94 * 1.5 = 10.41 at least(no meet!)
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// need to set 'r_cfg_chd' = ceil(ceil(20 / 6.94) - 1.5) * 2 = 3, reset value is '4'
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// for lower freq, can modify this value for performance tuning
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//
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// tSP(min: 2ns) is meet
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// data keeps 6.94 / 2 = 3.47ns low at least befer sclk
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`ifndef NMI_PSRAM_DEF_SV
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`define NMI_PSRAM_DEF_SV
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// verilog_format: off
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`define NMI_PSRAM_WAIT 8'h00
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`define NMI_PSRAM_CHD 8'h04
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`define NMI_PSRAM_INIT 8'h08
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// verilog_format: on
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`endif
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`include "mmap_define.svh"
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interface psram_if ();
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logic sck_o;
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logic [3:0] nss_o;
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logic [3:0] io_oe_o;
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logic [3:0] io_di_i;
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logic [3:0] io_do_o;
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logic irq_o;
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modport dut(
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output sck_o,
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output nss_o,
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output io_oe_o,
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input io_di_i,
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output io_do_o,
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output irq_o
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);
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endinterface
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module nmi_psram (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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nmi_if.slave nmi,
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psram_if.dut psram
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// verilog_format: on
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);
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// verilog_format: off
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localparam FSM_IDLE = 6'd0;
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localparam FSM_WE_ST = 6'd1;
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localparam FSM_WE = 6'd2;
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localparam FSM_RD_ST = 6'd3;
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localparam FSM_RD = 6'd4;
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// verilog_format: on
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// reg
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logic [ 4:0] r_cfg_wait;
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logic [ 2:0] r_cfg_chd;
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logic r_cfg_init;
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logic s_cfg_reg_sel;
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logic s_mem_sel;
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logic s_mem_ready;
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logic [31:0] s_mem_rdata;
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logic r_rd_st;
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logic r_wr_st;
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logic [ 7:0] r_xfer_data_bit_cnt;
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logic [ 5:0] r_fsm_state;
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logic [23:0] r_mem_addr;
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logic [31:0] r_mem_wdata;
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logic s_psram_ce;
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logic s_psram_sio_oen;
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logic [ 1:0] s_disp_addr_ofst;
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logic [ 7:0] s_disp_xfer_bit_cnt;
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logic [31:0] s_disp_wdata;
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logic s_init_done;
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logic s_core_idle;
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logic s_mem_valid_re;
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// verilog_format: off
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assign psram.nss_o[0] = (~s_init_done) || (s_init_done && nmi.addr[24:23] == 2'd0) ? s_psram_ce : 1'b1;
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assign psram.nss_o[1] = (~s_init_done) || (s_init_done && nmi.addr[24:23] == 2'd1) ? s_psram_ce : 1'b1;
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assign psram.nss_o[2] = (~s_init_done) || (s_init_done && nmi.addr[24:23] == 2'd2) ? s_psram_ce : 1'b1;
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assign psram.nss_o[3] = (~s_init_done) || (s_init_done && nmi.addr[24:23] == 2'd3) ? s_psram_ce : 1'b1;
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assign psram.io_oe_o[0] = ~s_psram_sio_oen;
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assign psram.io_oe_o[1] = ~s_psram_sio_oen;
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assign psram.io_oe_o[2] = ~s_psram_sio_oen;
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assign psram.io_oe_o[3] = ~s_psram_sio_oen;
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assign psram.irq_o = 1'b0;
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// verilog_format: on
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assign s_mem_sel = `SOC_ADDR_IS_PSRAM(nmi.addr);
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assign s_cfg_reg_sel = `SOC_ADDR_IS_NMI_PSRAM(nmi.addr);
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assign nmi.ready = s_mem_sel ? s_mem_ready : 1'b1;
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always_comb begin
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nmi.rdata = '0;
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if (s_mem_sel) begin
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nmi.rdata = s_mem_rdata;
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end else if (nmi.addr[7:0] == `NMI_PSRAM_WAIT) begin
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nmi.rdata = {27'd0, r_cfg_wait};
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end else if (nmi.addr[7:0] == `NMI_PSRAM_CHD) begin
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nmi.rdata = {29'd0, r_cfg_chd};
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end else if (nmi.addr[7:0] == `NMI_PSRAM_INIT) begin
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nmi.rdata = {31'd0, r_cfg_init};
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end
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end
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// wait cycles(mmio)
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always_ff @(posedge clk_i, negedge rst_n_i) begin
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if (~rst_n_i) r_cfg_wait <= 5'd18;
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else if (nmi.valid && nmi.wstrb[0] && s_cfg_reg_sel && nmi.addr[7:0] == `NMI_PSRAM_WAIT) begin
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r_cfg_wait <= nmi.wdata[4:0];
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end
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end
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// extra cycle for tCHD(mmio)
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always_ff @(posedge clk_i, negedge rst_n_i) begin
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if (~rst_n_i) r_cfg_chd <= 3'd4;
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else if (nmi.valid && nmi.wstrb[0] && s_cfg_reg_sel && nmi.addr[7:0] == `NMI_PSRAM_CHD) begin
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r_cfg_chd <= nmi.wdata[2:0];
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end
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end
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// init device/switch qpi mode
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always_ff @(posedge clk_i, negedge rst_n_i) begin
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if (~rst_n_i) r_cfg_init <= '0;
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else if (nmi.valid && nmi.wstrb[0] && s_cfg_reg_sel && nmi.addr[7:0] == `NMI_PSRAM_INIT) begin
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r_cfg_init <= nmi.wdata[0];
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end
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end
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edge_det_sync_re #(1) u_mem_valid_edge_det_sync_re (
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clk_i,
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rst_n_i,
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nmi.valid,
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s_mem_valid_re
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);
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always_ff @(posedge clk_i, negedge rst_n_i) begin
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if (~rst_n_i) begin
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r_rd_st <= '0;
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r_wr_st <= '0;
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r_xfer_data_bit_cnt <= '0;
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r_fsm_state <= FSM_IDLE;
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r_mem_addr <= '0;
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r_mem_wdata <= '0;
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end else begin
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if (s_mem_sel) begin
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/* verilator lint_off CASEINCOMPLETE */
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case (r_fsm_state)
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FSM_IDLE: begin
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if (s_mem_valid_re && (|nmi.wstrb)) begin
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r_fsm_state <= FSM_WE_ST;
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r_xfer_data_bit_cnt <= s_disp_xfer_bit_cnt;
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r_mem_addr <= {1'b0, nmi.addr[22:0]} + {22'd0, s_disp_addr_ofst};
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r_mem_wdata <= s_disp_wdata;
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end else if (s_mem_valid_re && (~(|nmi.wstrb))) begin
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r_fsm_state <= FSM_RD_ST;
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r_xfer_data_bit_cnt <= 8'd32;
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r_mem_addr <= {1'b0, nmi.addr[22:0]};
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r_mem_wdata <= nmi.wdata; // NOTE: no used
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end
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end
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FSM_WE_ST: begin
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if (s_core_idle) begin
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r_wr_st <= 1'b1;
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r_fsm_state <= FSM_WE;
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end
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end
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FSM_WE: begin
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r_wr_st <= 1'b0;
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if (s_mem_ready) r_fsm_state <= FSM_IDLE;
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end
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FSM_RD_ST: begin
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if (s_core_idle) begin
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r_rd_st <= 1'b1;
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r_fsm_state <= FSM_RD;
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end
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end
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FSM_RD: begin
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r_rd_st <= 1'b0;
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if (s_mem_ready) r_fsm_state <= FSM_IDLE;
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end
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endcase
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end
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end
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end
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psram_core u_psram_core (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.cfg_wait_i (r_cfg_wait),
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.cfg_chd_i (r_cfg_chd),
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.cfg_init_i (r_cfg_init),
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.mem_ready_o (s_mem_ready),
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.mem_addr_i (r_mem_addr),
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.mem_wdata_i (r_mem_wdata),
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.mem_rdata_o (s_mem_rdata),
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.xfer_data_bit_cnt_i(r_xfer_data_bit_cnt),
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.rd_st_i (r_rd_st),
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.wr_st_i (r_wr_st),
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.init_done_o (s_init_done),
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.idle_o (s_core_idle),
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.psram_sclk_o (psram.sck_o),
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.psram_ce_o (s_psram_ce),
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.psram_mosi_i (psram.io_di_i[0]),
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.psram_miso_i (psram.io_di_i[1]),
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.psram_sio2_i (psram.io_di_i[2]),
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.psram_sio3_i (psram.io_di_i[3]),
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.psram_mosi_o (psram.io_do_o[0]),
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.psram_miso_o (psram.io_do_o[1]),
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.psram_sio2_o (psram.io_do_o[2]),
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.psram_sio3_o (psram.io_do_o[3]),
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.psram_sio_oen_o (s_psram_sio_oen)
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);
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wr_dispatcher u_wr_dispatcher (
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.wstrb_i (nmi.wstrb),
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.wdata_i (nmi.wdata),
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.addr_ofst_o (s_disp_addr_ofst),
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.xfer_bit_cnt_o(s_disp_xfer_bit_cnt),
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.wdata_o (s_disp_wdata)
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);
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endmodule
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module wr_dispatcher (
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input logic [ 3:0] wstrb_i,
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input logic [31:0] wdata_i,
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output logic [ 1:0] addr_ofst_o,
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output logic [ 7:0] xfer_bit_cnt_o,
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output logic [31:0] wdata_o
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);
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always_comb begin
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wdata_o = wdata_i;
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case (wstrb_i)
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4'b0001: begin
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addr_ofst_o = 2'd0;
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xfer_bit_cnt_o = 8'd8;
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wdata_o[7:0] = wdata_i[7:0];
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end
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4'b0010: begin
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addr_ofst_o = 2'd1;
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xfer_bit_cnt_o = 8'd8;
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wdata_o[7:0] = wdata_i[15:8];
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end
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4'b0100: begin
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addr_ofst_o = 2'd2;
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xfer_bit_cnt_o = 8'd8;
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wdata_o[7:0] = wdata_i[23:16];
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end
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4'b1000: begin
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addr_ofst_o = 2'd3;
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xfer_bit_cnt_o = 8'd8;
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wdata_o[7:0] = wdata_i[31:24];
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end
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4'b0011: begin
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addr_ofst_o = 2'd0;
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xfer_bit_cnt_o = 8'd16;
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wdata_o[15:0] = wdata_i[15:0];
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end
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4'b1100: begin
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addr_ofst_o = 2'd2;
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xfer_bit_cnt_o = 8'd16;
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wdata_o[15:0] = wdata_i[31:16];
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end
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4'b1111: begin
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addr_ofst_o = 2'd0;
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xfer_bit_cnt_o = 8'd32;
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wdata_o[31:0] = wdata_i[31:0];
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end
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default: begin
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addr_ofst_o = 2'd0;
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xfer_bit_cnt_o = 8'd32;
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wdata_o = wdata_i[31:0];
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end
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endcase
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end
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endmodule
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