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https://github.com/retroSoC/retroSoC.git
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maksyuki
fc6440989f
- Introduced to define the development environment and validate runtime/platform contracts. - Enhanced with to ensure change markers adhere to publication rules. - Updated to integrate boot acceptance checks and ensure dependencies are correctly managed. - Added tests for environment validation, publication change scope, and CI stages to prevent regression and ensure compliance with publication standards. - Implemented checks in to validate the presence of development environment dependencies. - Refactored existing tests to improve coverage and ensure accurate validation of publication claims and software configurations.
77 lines
6.2 KiB
Typst
77 lines
6.2 KiB
Typst
#import "../style.typ": *
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#change-start("v05-emphasis-bus-programming","Selected body emphasis: bus programming")
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#let programming = data.system_reference.programming
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=== Bus Transaction Rules and Arbitration <bus-programming>
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The usable transaction set is the *intersection of the issuing master, fabric, adapters and
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destination*. A 64-bit fabric does not make every target a 64-bit register interface. Keep
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device/MMIO accesses within the target's register contract even when a bus path accepts a wider request.
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#ds-table("bus-path-rules",[Transaction rules by path in the reviewed implementation],
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([Path],[Admission / ordering],[Application constraint]),
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(([LP control fabric],[Aligned 1/2/4-byte beats; FIXED/INCR and legal 2/4/8/16-beat WRAP; at most 16 beats. One active transaction per master.],[Stay in one 4 KiB page and decoded target; locked transfers are rejected.]),
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([HP data crossbar],[Up to 8-byte beats; unlocked FIXED/INCR or legal WRAP lengths; checks the computed last address against the 4 KiB limit.],[Target and adapter limits still apply. The crossbar admission predicate alone is not a guarantee of arbitrary unaligned or 256-beat target transfers.]),
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([HP MMIO],[Downsized to AXI32 and crossed into the LP control path. Root write policy remains enforced.],[Use register width and side effects; do not infer system-wide exclusive/atomic support.]),
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([Memory adapters],[Preserve byte lanes, response identity and the supported target transaction contract across width/clock conversion.],[Observe each memory controller's burst, device/page and alignment restrictions.]),
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([APB4 register targets],[One register access with PSTRB/PSLVERR semantics defined by that IP.],[No APB burst assumption; unsupported offsets, strobes or busy writes can fail.])),
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widths:(0.85fr,1.8fr,1.5fr))
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The LP fabric explicitly checks natural alignment and the start/end target. The current native
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crossbar's #code("burst_legal") predicate is different: it rejects #code("AxLOCK"), limits
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beat size and burst encoding, and checks its computed address span. It must not be treated as
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a complete implementation of every AXI4 feature. Portable software uses naturally aligned
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transfers and the narrower documented target limits. See @register-programming for MMIO exceptions.
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==== Outstanding credits and identity
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#ds-table("master-credits",[Normal master credits extracted from the crossbar functions],
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([Slot / initiator],[Read credits],[Write credits],[Interpretation]),
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data.policies.map(p=>([#p.index / #code(p.name)],str(programming.read_credits.at(p.index)),
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str(programming.write_credits.at(p.index)),
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if programming.read_credits.at(p.index)==0 and programming.write_credits.at(p.index)==0
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{[No normal address admission through this slot.]} else {[Subject to target credits, ID and lifecycle gates.]})),
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widths:(1.5fr,0.55fr,0.6fr,1.65fr))
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SRAM and SDRAM have separate four-read/two-write target limits; serial and error targets use
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one read/one write. *Target credits and master credits both constrain admission*. The source
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identity receives a fixed master prefix, and the same source ID is blocked while its earlier
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transaction remains active. *Multiple IDs do not remove ordering requirements* imposed by software.
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The JPEG private path is connected to slot 6 in #code("soc_data_plane") and receives one normal
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read credit plus one normal write credit. Normal JPEG payload addresses remain subject to target
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policy, source-ID, lifecycle, and non-cacheable requirements. Error handling uses a separate
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credit allowance and does not weaken normal-path containment. This bounded admission repair does
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not qualify a complete JPEG workload, board behavior, or performance; see @known-limitations.
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==== Arbitration and its assumptions
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Read and write arbitration are separate per target. The normal base priorities are HP I/D 12,
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I/O gateways 10, DMA/JPEG/EXT-H/GA2D/NPU 8 and LP gateway 2; unassigned slots use priority zero.
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Incoming QoS can raise eligible normal requests to 15, except GA2D and NPU, whose base class remains 8
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and does not consume its incoming QoS. Age promotion still applies. Continuously eligible requests age to priority
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16 after the configured 256-cycle interval, while LP recovery receives priority 31.
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These priorities choose among eligible requests. A full credit count, a busy source ID,
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blocked resource, unavailable target or withheld handshake can prevent eligibility or progress.
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The aging interval is not a worst-case application latency. Report target readiness,
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contention, clock and outstanding state when interpreting wait counters.
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==== Error and retry behavior
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The LP path distinguishes unmapped decode errors from illegal/denied transaction errors.
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The native data plane can route denied accesses to a finite error target and record source
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attribution. A target timeout can trigger synthetic error completion and fail-closed isolation.
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Do not blindly retry a write with side effects after a timeout: first determine whether the
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target accepted it, preserve the fault and complete the documented recovery/reset sequence.
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Admission policy and a completed error response do not guarantee recovery of partially modified data.
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#source-note("rtl/mini/top/axi4_interconnect.sv",title:"Actual LP alignment, burst and target checks")
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#source-note("rtl/mini/top/axi4_data_crossbar.sv",title:"Native admission, credit and arbitration functions")
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#source-note("rtl/mini/top/soc_data_plane.sv",title:"Private masters, prefixes, gateways and CDC wiring")
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==== Long bursts through the 64-to-32-bit converter
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An aligned 64-bit INCR request longer than eight beats is split into sequential legal narrow
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transactions, each of at most sixteen 32-bit beats. Reads are reassembled into the original
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64-bit response sequence; writes collect the narrow responses into one response for the
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original request. This conversion does not remove source/target alignment, 4 KiB boundary,
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permission or length restrictions. It also does not raise the NPU's independently configured
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eight-beat maximum. Verify the source master, converter and final memory contract together.
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#source-note("rtl/mini/top/axi4_downsizer_64to32.sv",title:"Implemented fragmentation, read reassembly and write response aggregation")
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#change-end("v05-emphasis-bus-programming")
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