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https://github.com/retroSoC/retroSoC.git
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maksyuki
fc6440989f
- Introduced to define the development environment and validate runtime/platform contracts. - Enhanced with to ensure change markers adhere to publication rules. - Updated to integrate boot acceptance checks and ensure dependencies are correctly managed. - Added tests for environment validation, publication change scope, and CI stages to prevent regression and ensure compliance with publication standards. - Implemented checks in to validate the presence of development environment dependencies. - Refactored existing tests to improve coverage and ensure accurate validation of publication claims and software configurations.
43 lines
2.8 KiB
Typst
43 lines
2.8 KiB
Typst
#import "../style.typ": *
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#change-start("v05-emphasis-device-compatibility","Selected body emphasis: device compatibility")
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==== External Memory and Device Compatibility <device-compatibility>
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The table distinguishes a controller protocol profile, a simulation model and a *qualified
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physical component*. Geometry or a similar command set is insufficient to establish drop-in
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compatibility. Device order codes, supply, speed grade and board timing must be reviewed together.
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#ds-table("external-device-profiles",[External-memory profiles and their evidence boundary],
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([Device / profile],[Protocol and geometry],[Initialization / compatibility condition]),
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data.system_reference.programming.devices.map(r=>(r.name,[#r.protocol \ #r.geometry],r.setup)),
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widths:(1fr,1.4fr,1.75fr))
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#ds-table("external-device-evidence",[Model coverage versus physical-device qualification],
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([Device / profile],[Model evidence indexed],[Board],[Silicon]),
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data.system_reference.programming.devices.map(r=>(r.name,r.model,r.board,r.silicon)),
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widths:(1.1fr,1.85fr,0.6fr,0.6fr))
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Model source and test availability are *not a reviewed passing run*. The fast XPI backend is
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specifically narrower than a pin-level flash model: it is useful for selected boot/regression
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work and must not qualify erase/program behavior, all LUT modes or board sampling margins.
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Before substituting a component, compare its reset state, command/address encoding, mode/dummy
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phases, latency configuration, page and chip boundaries, supported sampling clocks and status
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bits. Validate the *complete initialization and recovery sequence*, not only a successful ID read.
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For SDRAM, match bank/row/column geometry and convert device timings to the actual memory clock.
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The QPI controller is device-specific. The OPI and modified single-clock HyperBus-style paths
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use different protocol encoders and are boot/profile-selected; they do not imply generic
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compatibility with every commercial octal or HyperBus device. A supplier's maximum device clock
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is not the characterized maximum frequency of the Mini-to-board interface.
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If no qualified device is listed, retain the profile/model status and obtain the missing
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component, board and timing evidence before releasing a BOM. Do not select an arbitrary
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commercial part merely to fill this table. Firmware must also respect @resource-conflicts,
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because QPI and OPI use mutually exclusive shared pads.
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#source-note("docs/ip/xpi.md",title:"XPI slot/LUT and full versus fast flash model")
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#source-note("docs/ip/psram.md",title:"ESP-PSRAM64H initialization and device boundaries")
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#source-note("docs/ip/opipsram.md",title:"Prototype OPI and single-clock HyperBus-style profiles")
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#source-note("docs/ip/sdram.md",title:"SDRAM geometry, clocking and timing configuration")
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#change-end("v05-emphasis-device-compatibility")
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