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https://github.com/retroSoC/retroSoC.git
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maksyuki
fc6440989f
- Introduced to define the development environment and validate runtime/platform contracts. - Enhanced with to ensure change markers adhere to publication rules. - Updated to integrate boot acceptance checks and ensure dependencies are correctly managed. - Added tests for environment validation, publication change scope, and CI stages to prevent regression and ensure compliance with publication standards. - Implemented checks in to validate the presence of development environment dependencies. - Refactored existing tests to improve coverage and ensure accurate validation of publication claims and software configurations.
102 lines
5.6 KiB
Typst
102 lines
5.6 KiB
Typst
#import "../style.typ": *
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#change-start("v05-emphasis-pins","Selected body emphasis: pins")
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== Packaging
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=== Pin Mapping
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The following inventory describes the *logical signal-pad ABI*. It *does not assign package pin
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numbers*, die-pad sequence numbers or FPGA ball locations. Numeric suffixes in bus signal names
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identify signal indices only. Power pads are technology-wrapper additions and are not assigned
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physical package numbers here.
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The reference profile disables PLL-dependent pads. Full GPIO pads carry data, output-enable
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and electrical controls. A top-level Verilog direction of `inout` may describe a pad-wrapper
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connection even for a functionally input-only signal; use the pad kind and interface contract
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together. Reset electrical properties require the selected PDK and board specification.
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#note[SDIO1 and USB2 ULPI have dedicated pad groups that are intentionally unbound in the generic
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FPGA wrapper until board pin locations, 3.3 V I/O-bank allocation and timing are approved.
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*Do not derive a package drawing from the order of rows* in this table.]
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#ds-table("pads", [Logical signal-pad inventory - reference profile],
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([Signal pad], [RTL direction], [Pad kind]),
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data.pads.map(p=>(code(p.name),p.direction,p.kind.replace("_"," "))),
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widths:(2.1fr,0.8fr,1.1fr),
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notes:[Physical Package Pin, Die Pad, power domain and electrical reset values: TBD.
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The inventory is generated from the canonical pin map.],
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)
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A released package mapping must bind each logical signal to a die pad, package pin, supply
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bank, pad-cell type and board net. Identify reset drive/enable and applicable electrical
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limits separately. Check pin uniqueness, intentional shared power connections and unbonded
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signals against the selected profile; row order and an FPGA ball assignment cannot supply
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this mapping. The matching physical release evidence is tracked in @release-verification.
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#pagebreak()
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=== GPIO Alternate-Function Matrix <gpio-mux>
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Each GPIO has software-controlled and alternate-function ownership. ALT0/ALT1 names below
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are normalized signal labels from the canonical topology. Shared names denote the same
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peripheral route; switching function also changes its input and output-enable connections.
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#ds-table("gpio-alt", [GPIO alternate functions],
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([GPIO], [ALT0], [ALT1]),
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data.gpio.map(g=>(str(g.pin),code(g.alt0_label),code(g.alt1_label))),
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widths:(0.35fr,1.55fr,1.55fr),
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notes:[GPIO0/1 multiplex UART0 flow control and PS/2. QPI and OPI share memory pads.
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Drivers must quiesce the old owner before changing pad mode.],
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)
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#include "connection-constraints.typ"
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=== Package Dimensions
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#placeholder[Package outline and mechanical dimensions]
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The old QFN128 and 12.3 × 12.3 mm description is not retained as a qualified mechanical
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specification. A package selection, approved outline, pin-1 orientation and thermal-pad
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connection must be supplied before a physical pinout is published.
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The mechanical record must identify the outline revision, top/bottom view, pin-1 orientation,
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body/lead dimensions and tolerances, seating plane and exposed-pad connection. Any CAD
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symbol, footprint or 3D model must name the same package revision. Those deliverables remain
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unprovided for this digital reference.
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=== Graded Reflow Soldering
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#tbd[Reflow profile, moisture sensitivity level, storage/bake requirements and permitted
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assembly excursions require the selected package supplier's qualified data.]
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=== Thermal and Reliability Information
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Publish thermal parameters only for an identified die, package and board condition. Junction-to-
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ambient, junction-to-case and characterization parameters are not interchangeable, and a
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typical board result is not a universal operating limit. No numerical thermal limit is attached
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to this digital reference.
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#ds-table("thermal-reliability",[Physical release information and required supporting evidence],
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([Topic],[Required supporting information],[State]),
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(([Thermal],[Package/die, board stackup, airflow, power map, method and applicable parameters.],[TBD]),
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([ESD / latch-up],[Pad/device configuration, method, stress levels and qualification results.],[TBD]),
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([Reliability],[Operating grade, lifetime assumptions, qualification plan and reports.],[TBD]),
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([Assembly],[Package materials, MSL, bake/storage and approved reflow profile.],[TBD]),
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([Physical identification],[Pin 1, die pads versus package pins, exposed pad and test/power connections.],[TBD])),
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widths:(0.75fr,2.85fr,0.4fr))
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Keep these fields separate from digital simulation and FPGA bringup results. Populate them
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from the chosen supplier/implementation reports before issuing a physical product specification.
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For each qualification entry, retain the method/revision, stress conditions, tested sample
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or lot population, result and applicable device/package grades. Thermal characterization
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also retains board construction and airflow. The verification summary in @release-verification
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keeps those physical records distinct from RTL tests and analytical estimates.
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=== Ordering Information
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#ds-table("ordering", [Ordering information awaiting qualification],
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([Field], [Specification]),
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(([Orderable part number], [TBD]),([Package / temperature grade], [TBD]),
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([Tape/reel and packing], [TBD]),([Availability / silicon revision], [TBD])),
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widths:(1fr,1fr),
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)
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An orderable-part record must connect its package and temperature grade to a documented
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die revision, marking scheme and packing option. Record applicable errata and ordering
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availability for that exact part. The source SHA and draft document version identify this
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publication; they are not a manufactured-device marking or a sales part number.
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#include "electrical-reference.typ"
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#change-end("v05-emphasis-pins")
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