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https://github.com/retroSoC/retroSoC.git
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maksyuki
fc6440989f
- Introduced to define the development environment and validate runtime/platform contracts. - Enhanced with to ensure change markers adhere to publication rules. - Updated to integrate boot acceptance checks and ensure dependencies are correctly managed. - Added tests for environment validation, publication change scope, and CI stages to prevent regression and ensure compliance with publication standards. - Implemented checks in to validate the presence of development environment dependencies. - Refactored existing tests to improve coverage and ensure accurate validation of publication claims and software configurations.
68 lines
5.7 KiB
Typst
68 lines
5.7 KiB
Typst
#import "../style.typ": *
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#change-start("v05-emphasis-processor-details","Selected body emphasis: processor details")
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#let cpu = data.system_reference.product_details.cpu
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=== Processor Configuration and Software-visible Capabilities <processor-details>
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The table separates the actual LP instance arguments, the explicit HP generator settings and
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the selected firmware build. It is a *configuration summary*, not a replacement for the CPU
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ISA/CSR manuals. A software compiler option does not remove a hardware extension or CSR block.
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#ds-table("processor-config",[Processor settings and the reference software configuration],
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([Property],[LP: instantiated Hazard3],[HP: explicit VexiiRiscv generator configuration]),
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(([Hart / role],[Hart 0; root management.],[Hart 1; application/Linux platform.]),
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([Execution width],[RV32 integration.],[XLEN #cpu.hp.xlen / physical address width #cpu.hp.physicalWidth.]),
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([Configured extensions],cpu.lp_extensions.join(", "),cpu.hp_isa.filter(x=>not(x in ("s","u"))).join(", ")),
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([Privilege],[Machine-mode configuration, U_MODE = #cpu.lp.U_MODE.],[S and U selected by the generator, in addition to machine-mode operation.]),
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([MMU / software platform],[No LP MMU is advertised by this integration.],[Supplied software platform declares Sv32; verify agreement with the generated core before deployment.]),
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([Protection],[PMP_REGIONS = #cpu.lp.PMP_REGIONS.],[PMP entries = #cpu.hp.at("pmpParam.pmpSize") / granularity = #cpu.hp.at("pmpParam.granularity") bytes.]),
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([Reset entry],code(data.reset_address),code(cpu.hp.resetVector.trim("L",at:end))),
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([Trap / counter configuration],[MTVEC_INIT: #code(cpu.lp.MTVEC_INIT) \ Machine CSR: #cpu.lp.CSR_M_MANDATORY / counters: #cpu.lp.CSR_COUNTER.],[ASID width #cpu.hp.asidWidth and #cpu.hp.additionalPerformanceCounters additional performance counters. \ Time-read option: #cpu.hp.at("privParam.withRdTime").]),
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([Debug],[DEBUG_SUPPORT = #cpu.lp.DEBUG_SUPPORT \ Breakpoint triggers: #cpu.lp.BREAKPOINT_TRIGGERS.],[Embedded JTAG/debug configured; triggers #cpu.hp.at("privParam.debugTriggers").]),
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([Issue configuration],[Use the selected Hazard3 instance and upstream core contract.],[#cpu.hp.decoders decoders and #cpu.hp.lanes lanes configured.])),
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widths:(0.8fr,1.6fr,1.75fr))
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The reference LP build uses #code(cpu.build.ISA) with #code("HAVE_CSR="+cpu.build.HAVE_CSR).
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Those build choices are separate from the instantiated LP extension and mandatory CSR settings.
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The HP profile selects #code(cpu.build.HP_CONFIG). OpenSBI, the device tree and the kernel
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configuration *must remain consistent with the core that is actually generated and used*.
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==== Cache geometry and evidence basis
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#ds-table("processor-cache-evidence",[Cache and generated-core evidence boundaries],
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([Item],[Recorded configuration],[Qualification]),
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(([HP instruction cache],[Enable setting #cpu.hp.fetchL1Enable with #cpu.hp.fetchL1Sets sets and #cpu.hp.fetchL1Ways ways; minimum memory data width #cpu.hp.fetchMemDataWidthMin bits.],[Explicit generator settings.]),
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([HP data cache],[Enable setting #cpu.hp.lsuL1Enable with #cpu.hp.lsuL1Sets sets and #cpu.hp.lsuL1Ways ways; minimum memory data width #cpu.hp.lsuMemDataWidthMin bits.],[Explicit generator settings.]),
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([Cache total capacity],cpu.hp_cache_capacity,[Sets multiplied by ways is *not a byte capacity* without the reviewed block size.]),
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([Cache maintenance],[Zicbom selected; supplied platform metadata declares a 64-byte CBO block.],[Keep platform metadata and the eventual generated implementation consistent.]),
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([Locked HP source],[#code(cpu.hp_revision.slice(0,12))],[The full dependency revision is recorded in the lock and publication manifest.]),
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([Generated HP artifact],cpu.generated_artifact_basis,[No new HP RTL generation or independent generated-manifest validation was performed for this publication.])),
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widths:(0.8fr,1.7fr,1.65fr))
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The current publication workspace does not supply the locked VexiiRiscv checkout and a matching
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generated-core manifest for independent inspection. Only explicit repository generator settings
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are listed as such. Upstream defaults, plugin expansion and derived byte capacities remain
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unconfirmed until that artifact/source evidence is attached. Do not relabel a configured feature
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as a tested generated-core or silicon capability.
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==== PMA coverage versus implemented memory
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#ds-table("hp-pma-coverage",[Explicit PMA envelopes in the HP generator],
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([Base],[Inclusive end],[Bytes],[Main memory],[Executable]),
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cpu.pma.map(r=>(code(r.base),code(r.end),str(r.bytes),r.main,r.executable)),
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widths:(1.1fr,1.1fr,0.8fr,0.65fr,0.65fr))
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A PMA envelope describes core-side attributes. It does not instantiate RAM or override the
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SoC decoder, per-master ACL, resource owner or physical device. In particular, the generator's
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SRAM attribute envelope is larger than the reference profile's 32 KiB physical SRAM region.
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Use the generated address map and selected profile for capacity and valid access bounds.
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Before deploying a new HP image, retain the lock revision, generator source, generated RTL/hash
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manifest and software build identity together. Check the core/device-tree feature agreement and
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the existing non-coherent buffer protocol. LP and HP configuration differences do not turn the
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two harts into a symmetric cache-coherent SMP platform.
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#block(above:rhythm.metadata-before,below:rhythm.metadata-after,breakable:false)[
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#set text(size:9pt)
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#source("rtl/mini/top/mgmt_core_wrapper.sv",title:"LP instance") ·
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#source("scripts/vexiiriscv/GenerateRetroSocHp.scala",title:"HP configuration/PMA") ·
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#source("scripts/generate_vexiiriscv.py",title:"Artifact manifest") ·
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#source("app/ports/linux/linux/retrosoc_hp.dts",title:"HP platform properties")
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]
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#change-end("v05-emphasis-processor-details")
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