mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
287 lines
9.7 KiB
Makefile
287 lines
9.7 KiB
Makefile
SHELL := /bin/bash
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.DEFAULT_GOAL := help
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.DELETE_ON_ERROR:
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ROOT_PATH ?= $(abspath $(dir $(firstword $(MAKEFILE_LIST))))
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CONFIG ?=
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LOCK_FILE ?= $(ROOT_PATH)/config/dependencies.lock.json
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ifneq ($(strip $(CONFIG)),)
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CONFIG_PATH := $(if $(filter /%,$(CONFIG)),$(CONFIG),$(ROOT_PATH)/$(CONFIG))
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ifeq ($(wildcard $(CONFIG_PATH)),)
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$(error Configuration profile not found: $(CONFIG_PATH))
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endif
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include $(CONFIG_PATH)
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PROFILE_NAME := $(basename $(notdir $(CONFIG_PATH)))
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else
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CONFIG_PATH :=
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PROFILE_NAME := manual
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endif
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SOC ?= MINI
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SIMU ?= VCS
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SYNTH ?= NONE
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STA ?= NONE
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# HW
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PDK ?= IHP130
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HAVE_PLL ?= NO
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HAVE_SRAM_IF ?= NO
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HAVE_SRAM_MACRO ?= NO
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HAVE_SVA ?= NO
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WAVE ?= NO
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RTL_SIM_CORESEL ?= 0
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RTL_SIM_TIMEOUT ?= -1
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SIM_FIRMWARE_NAME ?= $(FIRMWARE_NAME)
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SIM_SUCCESS_MARKER ?= retroSoC: A Customized ASIC for Retro Stuff
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RTL_PATH := $(ROOT_PATH)/rtl/mini
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CORE ?= HAZARD3
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IP ?= NONE
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RTL_TOP ?= retrosoc_tb
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# SW
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ISA ?= RV32IM
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HAVE_CSR ?= NO
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FIRMWARE_NAME ?= retrosoc_fw
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APP ?= shell
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LINK_TYPE ?= ld2_sram
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BUILD_ROOT ?= $(ROOT_PATH)/build
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CACHE_ROOT ?= $(ROOT_PATH)/.cache/retrosoc
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MAX_JOBS ?= 16
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HOST_CC ?= cc
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CLANG_FORMAT ?= clang-format-14
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JOBS ?= $(shell count=$$(nproc 2>/dev/null || printf '1'); \
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if [ "$$count" -gt "$(MAX_JOBS)" ]; then printf '%s' '$(MAX_JOBS)'; \
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else printf '%s' "$$count"; fi)
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CONFIG_KEY_VARS := SOC CORE IP PDK HAVE_PLL HAVE_SRAM_IF HAVE_SRAM_MACRO HAVE_SVA \
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ISA HAVE_CSR APP LINK_TYPE RTL_TOP FIRMWARE_NAME
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VARIANT_ID := $(strip $(shell python3 $(ROOT_PATH)/scripts/config_key.py \
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--lock $(LOCK_FILE) --profile $(PROFILE_NAME) \
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$(foreach var,$(CONFIG_KEY_VARS),--value $(var)=$($(var)))))
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ifeq ($(VARIANT_ID),)
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$(error Failed to calculate build variant ID)
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endif
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LOCK_DIGEST := $(strip $(shell python3 $(ROOT_PATH)/scripts/dependency_lock.py --lock $(LOCK_FILE) --digest))
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VARIANT_ROOT := $(abspath $(BUILD_ROOT))/$(VARIANT_ID)
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SW_BUILD_DIR := $(VARIANT_ROOT)/sw
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SIM_TOOL_NAME := $(shell printf '%s' '$(SIMU)' | tr '[:upper:]' '[:lower:]')
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SIM_BUILD_ROOT := $(VARIANT_ROOT)/sim/$(SIM_TOOL_NAME)
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SYN_BUILD_ROOT := $(VARIANT_ROOT)/syn/yosys
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STA_BUILD_ROOT := $(VARIANT_ROOT)/sta/opensta
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META_DIR := $(VARIANT_ROOT)/meta
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ifeq ($(SYNTH),YOSYS)
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FLOW_FILELIST_DIR := $(SYN_BUILD_ROOT)/filelists
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else
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FLOW_FILELIST_DIR := $(SIM_BUILD_ROOT)/filelists
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endif
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VALID_SOC := MINI
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VALID_CORE := PICORV32 HAZARD3 MDD
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VALID_IP := NONE MDD
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VALID_SIMU := VCS VERILATOR IVERILOG
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VALID_SYNTH := NONE YOSYS
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VALID_STA := NONE OPENSTA
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VALID_PDK := ICS55 IHP130 SKY130 GF180
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VALID_BOOL := YES NO
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VALID_ISA := RV32E RV32I RV32IM
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VALID_APP := bringup shell
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VALID_LINK_TYPE := xip ld2_sram ld2_psram ld2_sdram
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define validate_value
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$(if $(filter $($(1)),$(2)),,$(error Invalid $(1)='$($(1))'; expected one of: $(2)))
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endef
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$(call validate_value,SOC,$(VALID_SOC))
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$(call validate_value,CORE,$(VALID_CORE))
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$(call validate_value,IP,$(VALID_IP))
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$(call validate_value,SIMU,$(VALID_SIMU))
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$(call validate_value,SYNTH,$(VALID_SYNTH))
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$(call validate_value,STA,$(VALID_STA))
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$(call validate_value,PDK,$(VALID_PDK))
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$(call validate_value,HAVE_PLL,$(VALID_BOOL))
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$(call validate_value,HAVE_SRAM_IF,$(VALID_BOOL))
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$(call validate_value,HAVE_SRAM_MACRO,$(VALID_BOOL))
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$(call validate_value,HAVE_SVA,$(VALID_BOOL))
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$(call validate_value,WAVE,$(VALID_BOOL))
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$(call validate_value,ISA,$(VALID_ISA))
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$(call validate_value,HAVE_CSR,$(VALID_BOOL))
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$(call validate_value,APP,$(VALID_APP))
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$(call validate_value,LINK_TYPE,$(VALID_LINK_TYPE))
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ifeq ($(SYNTH),YOSYS)
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ifeq ($(filter $(PDK),IHP130 ICS55),)
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$(error Yosys synthesis supports PDK=IHP130 or PDK=ICS55, not PDK=$(PDK))
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endif
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endif
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ifeq ($(STA),OPENSTA)
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ifneq ($(PDK),IHP130)
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$(error OpenSTA currently supports PDK=IHP130 only)
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endif
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endif
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DEF_LIST ?= +define+PDK_$(PDK)
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DEF_LIST += +define+CORE_$(CORE)
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DEF_LIST += +define+IP_$(IP)
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DEF_LIST += +define+SIMU_$(SIMU)
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ifeq ($(HAVE_PLL), YES)
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DEF_LIST += +define+HAVE_PLL
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endif
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ifeq ($(HAVE_SRAM_IF), YES)
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DEF_LIST += +define+HAVE_SRAM_IF
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endif
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ifeq ($(HAVE_SRAM_MACRO), YES)
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DEF_LIST += +define+HAVE_SRAM_MACRO
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endif
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ifeq ($(HAVE_SVA), NO)
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DEF_LIST += +define+SV_ASSRT_DISABLE
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endif
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ifeq ($(SYNTH), YOSYS)
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DEF_LIST += +define+SYNTHESIS
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endif
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include rtl/mini/Makefile
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ifeq ($(SYNTH), YOSYS)
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include syn/yosys/yosys.mk
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endif
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ifeq ($(STA), OPENSTA)
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include sta/opensta/opensta.mk
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endif
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.PHONY: help config doctor setup setup-mpw setup-core setup-clusterip setup-ip setup-pdk setup-app \
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clean-all purge-cache manifest check-warnings metrics check-metrics package \
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regress-pr regress-nightly sim-asm sw-format sw-format-check sw-policy-check sw-host-test
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.NOTPARALLEL: setup
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help:
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@printf '%s\n' \
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'retroSoC build targets:' \
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' firmware | asm build firmware' \
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' comp | sim behavioral simulation' \
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' sim-asm build/run the assembly self-test' \
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' netcomp | netsim synthesized-netlist simulation' \
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' postcomp | postsim post-layout simulation' \
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' synth | sta synthesis and timing analysis' \
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' setup install pinned external dependencies' \
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' doctor check tools, paths, and selected configuration' \
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' config | manifest print/write the effective configuration' \
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' memory-map generate the selected address-map artifacts' \
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' check-memory-map validate the canonical address map' \
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' check-warnings | metrics analyze flow logs and reports' \
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' check-metrics apply the committed metrics policy' \
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' sw-format apply clang-format to self-owned embedded C code' \
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' sw-format-check check embedded C whitespace and line-ending policy' \
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' sw-policy-check check embedded C API and naming policy' \
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' sw-host-test run host tests for deterministic SDK utilities' \
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' regress-pr | regress-nightly run supported regression suites' \
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' package create checksummed source deliverables' \
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' clean | clean-all clean current flow or all build output' \
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' purge-cache remove dependency and compiler caches' \
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'' \
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'Usage: make CONFIG=configs/ci/hazard3-rv32im-ihp130.mk SIMU=IVERILOG sim'
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config:
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@printf '%-18s %s\n' \
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ROOT_PATH '$(ROOT_PATH)' CONFIG '$(or $(CONFIG_PATH),<defaults>)' \
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VARIANT_ID '$(VARIANT_ID)' VARIANT_ROOT '$(VARIANT_ROOT)' \
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JOBS '$(JOBS)' \
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SOC '$(SOC)' CORE '$(CORE)' IP '$(IP)' \
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SIMU '$(SIMU)' SYNTH '$(SYNTH)' STA '$(STA)' PDK '$(PDK)' \
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HAVE_PLL '$(HAVE_PLL)' HAVE_SRAM_IF '$(HAVE_SRAM_IF)' \
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HAVE_SRAM_MACRO '$(HAVE_SRAM_MACRO)' HAVE_SVA '$(HAVE_SVA)' \
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ISA '$(ISA)' HAVE_CSR '$(HAVE_CSR)' APP '$(APP)' \
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LINK_TYPE '$(LINK_TYPE)'
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doctor:
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@python3 $(ROOT_PATH)/scripts/doctor.py \
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--root $(ROOT_PATH) --simu $(SIMU) --synth $(SYNTH) --sta $(STA) \
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--pdk $(PDK) --core $(CORE) --ip $(IP) --lock $(LOCK_FILE)
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setup: setup-mpw setup-core setup-clusterip setup-ip setup-pdk setup-app
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setup-mpw:
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python3 $(ROOT_PATH)/setup.py
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python3 $(ROOT_PATH)/scripts/prepare_mpw.py \
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--lock-file $(CACHE_ROOT)/locks/mpw-prepare.lock
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@mkdir -p $(dir $(MPW_STAMP))
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@touch $(MPW_STAMP)
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setup-core: setup-mpw
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python3 $(ROOT_PATH)/rtl/mini/script/prepare_picorv32.py
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setup-clusterip:
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python3 $(ROOT_PATH)/rtl/managed/clusterip/setup.py
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setup-ip:
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python3 $(ROOT_PATH)/rtl/ip/setup.py
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setup-pdk:
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python3 $(ROOT_PATH)/pdk/setup.py --pdk $(PDK)
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setup-app:
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python3 $(ROOT_PATH)/app/setup.py
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clean-all:
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python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(abspath $(BUILD_ROOT))
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purge-cache:
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python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(abspath $(CACHE_ROOT))
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manifest:
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python3 $(ROOT_PATH)/scripts/manifest.py create --root $(ROOT_PATH) \
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--lock $(LOCK_FILE) --output $(META_DIR)/manifest.json --profile $(PROFILE_NAME) \
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$(foreach var,$(CONFIG_KEY_VARS),--config $(var)=$($(var))) \
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--config SIMU=$(SIMU) --config SYNTH=$(SYNTH) --config STA=$(STA)
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check-warnings:
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python3 $(ROOT_PATH)/scripts/analyze_warnings.py check --root $(ROOT_PATH) \
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--profile $(PROFILE_NAME) --variant-root $(VARIANT_ROOT) --output $(META_DIR)/warnings.json
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metrics:
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python3 $(ROOT_PATH)/scripts/metrics.py collect --variant-root $(VARIANT_ROOT) \
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--output $(META_DIR)/metrics.json
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check-metrics: metrics
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python3 $(ROOT_PATH)/scripts/metrics.py check --metrics $(META_DIR)/metrics.json \
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--policy $(ROOT_PATH)/quality/metrics/policy.json \
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--baseline $(ROOT_PATH)/quality/metrics/baseline.json
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sw-format:
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python3 $(ROOT_PATH)/scripts/check_embedded_c.py --root $(ROOT_PATH) \
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--apply-format --clang-format $(CLANG_FORMAT)
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sw-format-check:
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python3 $(ROOT_PATH)/scripts/check_embedded_c.py --root $(ROOT_PATH) --format-check \
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--clang-format-check --clang-format $(CLANG_FORMAT)
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sw-policy-check:
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python3 $(ROOT_PATH)/scripts/check_embedded_c.py --root $(ROOT_PATH) --policy-check
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sw-host-test:
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python3 $(ROOT_PATH)/scripts/run_c_tests.py --root $(ROOT_PATH) --cc $(HOST_CC)
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package: $(MPW_VARIANT_STAMP) $(FILELIST_STAMP) manifest
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python3 $(ROOT_PATH)/scripts/package.py --root $(ROOT_PATH) --lock $(LOCK_FILE) \
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--variant-root $(VARIANT_ROOT) --output-dir $(ROOT_PATH)/dist/$(VARIANT_ID)
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regress-pr:
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python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite pr
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regress-nightly:
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python3 $(ROOT_PATH)/scripts/regress.py --root $(ROOT_PATH) --suite nightly
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sim-asm: asm
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$(MAKE) SIM_FIRMWARE_NAME=$(ASM_FIRMWARE_NAME) \
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SIM_SUCCESS_MARKER='Mem wr/rd test success' sim
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