mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
35 lines
822 B
C
35 lines
822 B
C
#ifndef RETROSOC_HAL_CLOCK_H
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#define RETROSOC_HAL_CLOCK_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <retrosoc/core/status.h>
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typedef enum {
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RS_CLOCK_FREQ_24MHZ = 0,
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RS_CLOCK_FREQ_48MHZ = 1,
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RS_CLOCK_FREQ_72MHZ = 2,
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RS_CLOCK_FREQ_96MHZ = 3,
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RS_CLOCK_FREQ_120MHZ = 4,
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RS_CLOCK_FREQ_144MHZ = 5,
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RS_CLOCK_FREQ_168MHZ = 6,
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RS_CLOCK_FREQ_192MHZ = 7,
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} rs_clock_frequency_t;
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typedef struct {
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rs_clock_frequency_t requested_frequency;
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rs_clock_frequency_t active_frequency;
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uint8_t error_reason;
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bool active_valid;
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bool busy;
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bool safe_clock;
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bool pll_locked;
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bool capable;
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} rs_clock_status_t;
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rs_status_t rs_clock_get_status(rs_clock_status_t *status);
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rs_status_t rs_clock_set_frequency(rs_clock_frequency_t frequency, rs_timeout_t timeout);
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#endif
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