maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
1.7 KiB
PLL Dynamic Clock Control
The system powers up on the extclk_i_pad external safe clock. After software
submits a PLL frequency request through SYSCTRL, the RCU switches to the safe
source, configures the PLL, waits for lock, and switches back in the external
reference-clock domain. PLL lock transitions do not reset the system. A failed
configuration leaves the system on the safe clock.
Registers
| Offset | Name | Access | Description |
|---|---|---|---|
0x08 |
PLL_CFG |
RW | FREQ_SEL[2:0]: 24, 48, 72, 96, 120, 144, 168, or 192 MHz. |
0x0c |
PLL_CMD |
WO | bit 0 is APPLY; bit 1 is CLEAR_ERROR. |
0x1c |
PLL_STATUS |
RO | Active profile, validity, busy state, error and cause, safe-clock source, lock state, and capability. |
Applications use rs_clock_set_frequency() and rs_clock_get_status() from
<retrosoc/hal/clock.h>; PDK-specific PLL divider settings are not exposed.
Software Flow
- Run the transition routine from SRAM, disable interrupts, and quiesce DMA, serial transfers, and other frequency-sensitive transactions.
- Call
rs_clock_set_frequency()and wait with a bounded timeout. - On success, reprogram UART, SPI, I2C, timer, and other divider-dependent peripherals for the new frequency before restoring normal operation.
RS_ENOTSUPmeans the current PDK has no integrated dynamic PLL or glitch-free clock-switch backend. The system remains on the external safe clock.
PDK_BEHAV provides a dynamic-frequency and lock behavior model. A real PDK
must integrate a characterized PLL macro, lock timing, and glitch-free clock
switch before setting capability to 1. The current IHP130 and ICS55 backends
do not advertise this capability.