mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
53 lines
1.5 KiB
Systemverilog
53 lines
1.5 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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interface pll_ctrl_if ();
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logic [2:0] req_sel_o;
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logic req_valid_o;
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logic req_ready_i;
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logic [2:0] rsp_active_sel_i;
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logic rsp_active_valid_i;
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logic rsp_safe_clk_i;
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logic rsp_pll_lock_i;
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logic [1:0] rsp_error_i;
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logic rsp_valid_i;
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logic rsp_ready_o;
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logic capable_i;
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modport sysctrl(
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output req_sel_o,
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output req_valid_o,
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output rsp_ready_o,
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input req_ready_i,
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input rsp_active_sel_i,
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input rsp_active_valid_i,
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input rsp_safe_clk_i,
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input rsp_pll_lock_i,
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input rsp_error_i,
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input rsp_valid_i,
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input capable_i
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);
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modport rcu(
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input req_sel_o,
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input req_valid_o,
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input rsp_ready_o,
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output req_ready_i,
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output rsp_active_sel_i,
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output rsp_active_valid_i,
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output rsp_safe_clk_i,
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output rsp_pll_lock_i,
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output rsp_error_i,
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output rsp_valid_i,
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output capable_i
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);
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endinterface
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