mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
307 lines
9.1 KiB
Systemverilog
307 lines
9.1 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`ifndef SYSCTEL_DEF_SV
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`define SYSCTEL_DEF_SV
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// verilog_format: off
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`define NATV_SYSCTRL_CORESEL 8'h00 // RO
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`define NATV_SYSCTRL_IPSEL 8'h04 // WR/RD
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`define NATV_SYSCTRL_PLL_CFG `SOC_SYSCTRL_PLL_CFG_OFFSET // WR/RD
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`define NATV_SYSCTRL_PLL_CMD `SOC_SYSCTRL_PLL_CMD_OFFSET // WO
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`define NATV_SYSCTRL_FAULT_STATUS `SOC_SYSCTRL_FAULT_STATUS_OFFSET // W1C/RD
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`define NATV_SYSCTRL_FAULT_ADDR `SOC_SYSCTRL_FAULT_ADDR_OFFSET // RD
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`define NATV_SYSCTRL_FAULT_COUNT `SOC_SYSCTRL_FAULT_COUNT_OFFSET // RD
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`define NATV_SYSCTRL_PLL_STATUS `SOC_SYSCTRL_PLL_STATUS_OFFSET // RD
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// verilog_format: on
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`endif
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`include "mdd_config.svh"
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`include "mmap_define.svh"
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interface sysctrl_if ();
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logic [`USER_CORESEL_WIDTH-1:0] core_sel_i;
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logic [ `USER_IPSEL_WIDTH-1:0] ip_sel_o;
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modport dut(input core_sel_i, output ip_sel_o);
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endinterface
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module nmi_sysctrl (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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input logic fault_valid_i,
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input logic [31:0] fault_addr_i,
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input logic [3:0] fault_wstrb_i,
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input logic fault_reserved_i,
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nmi_if.slave nmi,
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sysctrl_if.dut sysctrl,
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pll_ctrl_if.sysctrl pll_ctrl
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// verilog_format: on
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);
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logic s_nmi_wr_hdshk, s_nmi_rd_hdshk;
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logic s_nmi_ready_d, s_nmi_ready_q;
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logic s_nmi_rdata_en;
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logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;
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logic [`USER_CORESEL_WIDTH-1:0] s_sysctrl_coresel_d, s_sysctrl_coresel_q;
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logic s_sysctrl_ipsel_en;
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logic [`USER_IPSEL_WIDTH-1:0] s_sysctrl_ipsel_d, s_sysctrl_ipsel_q;
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logic [2:0] s_pll_cfg_d, s_pll_cfg_q;
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logic s_pll_cfg_en;
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logic s_pll_apply, s_pll_clear_error;
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logic s_pll_req_valid_d, s_pll_req_valid_q;
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logic s_pll_busy_d, s_pll_busy_q;
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logic s_pll_rsp_accept;
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logic s_pll_error_d, s_pll_error_q;
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logic [1:0] s_pll_error_reason_d, s_pll_error_reason_q;
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logic [2:0] s_pll_active_sel_d, s_pll_active_sel_q;
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logic s_pll_active_valid_d, s_pll_active_valid_q;
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logic s_pll_safe_clk_d, s_pll_safe_clk_q;
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logic s_pll_lock_d, s_pll_lock_q;
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logic s_fault_status_clear;
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logic s_fault_pending_d, s_fault_pending_q;
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logic s_fault_write_d, s_fault_write_q;
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logic [1:0] s_fault_reason_d, s_fault_reason_q;
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logic [31:0] s_fault_addr_d, s_fault_addr_q;
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logic [31:0] s_fault_count_d, s_fault_count_q;
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assign s_nmi_wr_hdshk = nmi.valid && (~s_nmi_ready_q) && (|nmi.wstrb);
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assign s_nmi_rd_hdshk = nmi.valid && (~s_nmi_ready_q) && (~(|nmi.wstrb));
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assign nmi.ready = s_nmi_ready_q;
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assign nmi.rdata = s_nmi_rdata_q;
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assign sysctrl.ip_sel_o = s_sysctrl_ipsel_q;
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assign pll_ctrl.req_sel_o = s_pll_cfg_q;
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assign pll_ctrl.req_valid_o = s_pll_req_valid_q;
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assign pll_ctrl.rsp_ready_o = 1'b1;
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assign s_sysctrl_coresel_d = sysctrl.core_sel_i;
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dffr #(`USER_CORESEL_WIDTH) u_sysctrl_coresel_dffr (
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clk_i,
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rst_n_i,
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s_sysctrl_coresel_d,
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s_sysctrl_coresel_q
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);
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assign s_sysctrl_ipsel_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_SYSCTRL_IPSEL;
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assign s_sysctrl_ipsel_d = nmi.wdata[`USER_IPSEL_WIDTH-1:0];
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dffer #(`USER_IPSEL_WIDTH) u_sysctrl_ipsel_dffer (
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clk_i,
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rst_n_i,
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s_sysctrl_ipsel_en,
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s_sysctrl_ipsel_d,
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s_sysctrl_ipsel_q
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);
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assign s_pll_cfg_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_SYSCTRL_PLL_CFG && nmi.wstrb[0];
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assign s_pll_cfg_d = nmi.wdata[2:0];
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dffer #(3) u_pll_cfg_dffer (
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clk_i,
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rst_n_i,
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s_pll_cfg_en,
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s_pll_cfg_d,
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s_pll_cfg_q
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);
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assign s_pll_apply = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_SYSCTRL_PLL_CMD &&
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nmi.wstrb[0] && nmi.wdata[0];
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assign s_pll_clear_error = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_SYSCTRL_PLL_CMD &&
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nmi.wstrb[0] && nmi.wdata[1];
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assign s_pll_rsp_accept = pll_ctrl.rsp_valid_i && pll_ctrl.rsp_ready_o;
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always_comb begin
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s_pll_req_valid_d = s_pll_req_valid_q;
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s_pll_busy_d = s_pll_busy_q;
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if (s_pll_req_valid_q && pll_ctrl.req_ready_i) begin
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s_pll_req_valid_d = 1'b0;
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end
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if (s_pll_apply && ~s_pll_busy_q && ~s_pll_req_valid_q) begin
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s_pll_req_valid_d = 1'b1;
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s_pll_busy_d = 1'b1;
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end
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if (s_pll_rsp_accept) begin
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s_pll_busy_d = 1'b0;
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end
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end
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dffr #(1) u_pll_req_valid_dffr (
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clk_i,
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rst_n_i,
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s_pll_req_valid_d,
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s_pll_req_valid_q
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);
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dffr #(1) u_pll_busy_dffr (
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clk_i,
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rst_n_i,
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s_pll_busy_d,
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s_pll_busy_q
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);
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always_comb begin
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s_pll_error_d = s_pll_error_q;
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s_pll_error_reason_d = s_pll_error_reason_q;
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if (s_pll_clear_error) begin
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s_pll_error_d = 1'b0;
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s_pll_error_reason_d = 2'd0;
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end
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if (s_pll_apply && (s_pll_busy_q || s_pll_req_valid_q)) begin
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s_pll_error_d = 1'b1;
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s_pll_error_reason_d = 2'd3;
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end
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if (s_pll_rsp_accept && |pll_ctrl.rsp_error_i) begin
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s_pll_error_d = 1'b1;
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s_pll_error_reason_d = pll_ctrl.rsp_error_i;
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end
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end
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dffr #(1) u_pll_error_dffr (
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clk_i,
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rst_n_i,
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s_pll_error_d,
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s_pll_error_q
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);
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dffr #(2) u_pll_error_reason_dffr (
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clk_i,
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rst_n_i,
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s_pll_error_reason_d,
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s_pll_error_reason_q
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);
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assign s_pll_active_sel_d = pll_ctrl.rsp_active_sel_i;
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dffer #(3) u_pll_active_sel_dffer (
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clk_i,
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rst_n_i,
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s_pll_rsp_accept,
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s_pll_active_sel_d,
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s_pll_active_sel_q
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);
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assign s_pll_active_valid_d = pll_ctrl.rsp_active_valid_i;
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dffer #(1) u_pll_active_valid_dffer (
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clk_i,
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rst_n_i,
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s_pll_rsp_accept,
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s_pll_active_valid_d,
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s_pll_active_valid_q
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);
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assign s_pll_safe_clk_d = pll_ctrl.rsp_safe_clk_i;
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dfferc #(1, 1'b1) u_pll_safe_clk_dfferc (
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clk_i,
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rst_n_i,
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s_pll_rsp_accept,
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s_pll_safe_clk_d,
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s_pll_safe_clk_q
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);
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assign s_pll_lock_d = pll_ctrl.rsp_pll_lock_i;
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dffer #(1) u_pll_lock_dffer (
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clk_i,
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rst_n_i,
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s_pll_rsp_accept,
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s_pll_lock_d,
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s_pll_lock_q
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);
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assign s_fault_status_clear = s_nmi_wr_hdshk &&
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nmi.addr[7:0] == `NATV_SYSCTRL_FAULT_STATUS &&
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nmi.wstrb[0] && nmi.wdata[0];
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always_comb begin
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s_fault_pending_d = s_fault_pending_q;
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s_fault_write_d = s_fault_write_q;
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s_fault_reason_d = s_fault_reason_q;
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s_fault_addr_d = s_fault_addr_q;
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s_fault_count_d = s_fault_count_q;
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if (s_fault_status_clear) begin
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s_fault_pending_d = 1'b0;
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end
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if (fault_valid_i) begin
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s_fault_pending_d = 1'b1;
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s_fault_write_d = |fault_wstrb_i;
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s_fault_reason_d = fault_reserved_i ? 2'd2 : 2'd1;
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s_fault_addr_d = fault_addr_i;
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if (~(&s_fault_count_q)) begin
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s_fault_count_d = s_fault_count_q + 32'd1;
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end
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end
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end
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dffr #(1) u_fault_pending_dffr (
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clk_i,
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rst_n_i,
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s_fault_pending_d,
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s_fault_pending_q
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);
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dffr #(1) u_fault_write_dffr (
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clk_i,
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rst_n_i,
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s_fault_write_d,
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s_fault_write_q
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);
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dffr #(2) u_fault_reason_dffr (
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clk_i,
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rst_n_i,
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s_fault_reason_d,
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s_fault_reason_q
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);
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dffr #(32) u_fault_addr_dffr (
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clk_i,
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rst_n_i,
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s_fault_addr_d,
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s_fault_addr_q
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);
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dffr #(32) u_fault_count_dffr (
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clk_i,
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rst_n_i,
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s_fault_count_d,
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s_fault_count_q
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);
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assign s_nmi_ready_d = nmi.valid && (~s_nmi_ready_q);
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dffr #(1) u_nmi_ready_dffr (
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clk_i,
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rst_n_i,
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s_nmi_ready_d,
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s_nmi_ready_q
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);
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assign s_nmi_rdata_en = s_nmi_rd_hdshk;
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always_comb begin
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s_nmi_rdata_d = s_nmi_rdata_q;
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unique case (nmi.addr[7:0])
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// verilog_format: off
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`NATV_SYSCTRL_CORESEL: s_nmi_rdata_d = {{(32 - `USER_CORESEL_WIDTH) {1'b0}}, s_sysctrl_coresel_q};
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`NATV_SYSCTRL_IPSEL: s_nmi_rdata_d = {{(32 - `USER_IPSEL_WIDTH) {1'b0}}, s_sysctrl_ipsel_q};
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`NATV_SYSCTRL_PLL_CFG: s_nmi_rdata_d = {29'd0, s_pll_cfg_q};
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`NATV_SYSCTRL_FAULT_STATUS: s_nmi_rdata_d = {28'd0, s_fault_reason_q, s_fault_write_q, s_fault_pending_q};
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`NATV_SYSCTRL_FAULT_ADDR: s_nmi_rdata_d = s_fault_addr_q;
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`NATV_SYSCTRL_FAULT_COUNT: s_nmi_rdata_d = s_fault_count_q;
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`NATV_SYSCTRL_PLL_STATUS: s_nmi_rdata_d = {
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21'd0,
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pll_ctrl.capable_i,
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s_pll_lock_q,
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s_pll_safe_clk_q,
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s_pll_error_reason_q,
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s_pll_error_q,
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s_pll_busy_q,
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s_pll_active_valid_q,
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s_pll_active_sel_q
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};
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default: s_nmi_rdata_d = s_nmi_rdata_q;
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endcase
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// verilog_format: on
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end
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dffer #(32) u_nmi_rdata_dffer (
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clk_i,
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rst_n_i,
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s_nmi_rdata_en,
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s_nmi_rdata_d,
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s_nmi_rdata_q
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);
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endmodule
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