mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
250 lines
9.5 KiB
Python
250 lines
9.5 KiB
Python
#!/usr/bin/env python3
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"""Generate RTL, SDK and linker address-map artifacts from one JSON source."""
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from __future__ import annotations
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import argparse
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import json
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import os
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import tempfile
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from pathlib import Path
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from typing import Any
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MAX_ADDRESS = 1 << 32
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VALID_ROUTES = {"native", "apb", "ram", "reserved"}
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VALID_KINDS = {"active", "reserved"}
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def parse_integer(value: Any, field: str) -> int:
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if isinstance(value, int):
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return value
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if isinstance(value, str):
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try:
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return int(value, 0)
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except ValueError as error:
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raise ValueError(f"{field} must be an integer: {value!r}") from error
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raise ValueError(f"{field} must be an integer")
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def read_map(path: Path) -> tuple[int, list[dict[str, Any]]]:
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with path.open(encoding="utf-8") as source:
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document = json.load(source)
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if document.get("schema_version") != 1:
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raise ValueError("schema_version must be 1")
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cpu_reset = parse_integer(document.get("cpu_reset"), "cpu_reset")
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regions = document.get("regions")
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if not isinstance(regions, list) or not regions:
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raise ValueError("regions must be a non-empty list")
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normalized: list[dict[str, Any]] = []
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symbols: set[str] = set()
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for index, region in enumerate(regions):
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if not isinstance(region, dict):
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raise ValueError(f"regions[{index}] must be an object")
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symbol = region.get("symbol")
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if not isinstance(symbol, str) or not symbol or not symbol.replace("_", "").isalnum():
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raise ValueError(f"regions[{index}].symbol must be an uppercase identifier")
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if symbol != symbol.upper() or symbol in symbols:
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raise ValueError(f"regions[{index}].symbol must be unique and uppercase")
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symbols.add(symbol)
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route = region.get("route")
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kind = region.get("kind")
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if route not in VALID_ROUTES or kind not in VALID_KINDS:
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raise ValueError(f"regions[{index}] has invalid route or kind")
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if (route == "reserved") != (kind == "reserved"):
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raise ValueError(f"regions[{index}] reserved route and kind must agree")
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requires_ip = region.get("requires_ip")
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if requires_ip is not None and requires_ip != "MDD":
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raise ValueError(f"regions[{index}].requires_ip must be MDD when present")
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base = parse_integer(region.get("base"), f"regions[{index}].base")
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size = parse_integer(region.get("size"), f"regions[{index}].size")
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if base < 0 or size <= 0 or base + size > MAX_ADDRESS:
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raise ValueError(f"regions[{index}] exceeds the 32-bit address space")
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if base % 4 != 0 or size % 4 != 0:
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raise ValueError(f"regions[{index}] must be 32-bit aligned")
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normalized.append(
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{
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"symbol": symbol,
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"base": base,
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"size": size,
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"end": base + size - 1,
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"route": route,
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"kind": kind,
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"public": region.get("public", False) is True,
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"linker": region.get("linker"),
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"requires_ip": requires_ip,
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}
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)
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previous: dict[str, Any] | None = None
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for region in sorted(normalized, key=lambda item: item["base"]):
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if previous is not None and region["base"] <= previous["end"]:
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raise ValueError(f"address-map overlap: {previous['symbol']} and {region['symbol']}")
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previous = region
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return cpu_reset, normalized
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def hex32(value: int) -> str:
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return f"32'h{value:08X}"
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def c_hex32(value: int) -> str:
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return f"UINT32_C(0x{value:08X})"
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def range_expression(symbol: str) -> str:
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return f"((addr) >= `SOC_ADDR_{symbol}_BASE && (addr) <= `SOC_ADDR_{symbol}_END)"
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def join_or(expressions: list[str]) -> str:
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return " || \\\n ".join(expressions) if expressions else "1'b0"
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def render_rtl(cpu_reset: int, regions: list[dict[str, Any]]) -> str:
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lines = [
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"// Generated by rtl/mini/address_map/generate_memory_map.py; do not edit.",
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"`ifndef RETROSOC_GENERATED_MMAP_DEFINE_SVH",
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"`define RETROSOC_GENERATED_MMAP_DEFINE_SVH",
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"",
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f"`define SOC_CPU_RESET_ADDR {hex32(cpu_reset)}",
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"`define SOC_IRQ_START_ADDR `SOC_CPU_RESET_ADDR",
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"// Compatibility aliases for managed MPW cores.",
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"`define CPU_RESET_ADDR `SOC_CPU_RESET_ADDR",
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"`define IRQ_START_ADDR `SOC_IRQ_START_ADDR",
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"",
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]
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for region in regions:
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symbol = region["symbol"]
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lines += [
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f"`define SOC_ADDR_{symbol}_BASE {hex32(region['base'])}",
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f"`define SOC_ADDR_{symbol}_END {hex32(region['end'])}",
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f"`define SOC_ADDR_IS_{symbol}(addr) {range_expression(symbol)}",
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]
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lines.append("")
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for route in ("native", "apb", "ram", "reserved"):
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selected = [
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f"`SOC_ADDR_IS_{region['symbol']}(addr)"
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for region in regions
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if region["route"] == route
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]
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lines.append(f"`define SOC_ADDR_IS_{route.upper()}(addr) ({join_or(selected)})")
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lines += [
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"",
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"`define SOC_SYSCTRL_PLL_CFG_OFFSET 32'h00000008",
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"`define SOC_SYSCTRL_PLL_CMD_OFFSET 32'h0000000C",
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"`define SOC_SYSCTRL_FAULT_STATUS_OFFSET 32'h00000010",
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"`define SOC_SYSCTRL_FAULT_ADDR_OFFSET 32'h00000014",
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"`define SOC_SYSCTRL_FAULT_COUNT_OFFSET 32'h00000018",
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"`define SOC_SYSCTRL_PLL_STATUS_OFFSET 32'h0000001C",
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"",
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"`endif",
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"",
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]
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return "\n".join(lines)
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def render_c(cpu_reset: int, regions: list[dict[str, Any]], have_sram_if: str) -> str:
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lines = [
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"/* Generated by rtl/mini/address_map/generate_memory_map.py; do not edit. */",
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"#ifndef RETROSOC_GENERATED_MEMORY_MAP_H",
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"#define RETROSOC_GENERATED_MEMORY_MAP_H",
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"",
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"#include <stdint.h>",
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"",
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f"#define RS_SOC_CPU_RESET_ADDR {c_hex32(cpu_reset)}",
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f"#define RS_SOC_HAS_SRAM {1 if have_sram_if == 'YES' else 0}U",
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"",
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]
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for region in regions:
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if not region["public"]:
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continue
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symbol = region["symbol"]
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lines += [
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f"#define RS_SOC_{symbol}_BASE {c_hex32(region['base'])}",
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f"#define RS_SOC_{symbol}_SIZE {c_hex32(region['size'])}",
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f"#define RS_SOC_{symbol}_END {c_hex32(region['end'])}",
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]
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lines += [
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"",
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"#define RS_SOC_SYSCTRL_PLL_CFG_OFFSET UINT32_C(0x00000008)",
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"#define RS_SOC_SYSCTRL_PLL_CMD_OFFSET UINT32_C(0x0000000C)",
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"#define RS_SOC_SYSCTRL_FAULT_STATUS_OFFSET UINT32_C(0x00000010)",
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"#define RS_SOC_SYSCTRL_FAULT_ADDR_OFFSET UINT32_C(0x00000014)",
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"#define RS_SOC_SYSCTRL_FAULT_COUNT_OFFSET UINT32_C(0x00000018)",
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"#define RS_SOC_SYSCTRL_PLL_STATUS_OFFSET UINT32_C(0x0000001C)",
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"",
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"#endif",
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"",
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]
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return "\n".join(lines)
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def render_linker(regions: list[dict[str, Any]]) -> str:
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lines = [
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"/* Generated by rtl/mini/address_map/generate_memory_map.py; do not edit. */",
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"MEMORY",
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"{",
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]
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for region in regions:
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linker = region["linker"]
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if linker is None:
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continue
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attributes = "rx" if linker == "FLASH" else "wxa!ri"
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lines.append(
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f" {linker} ({attributes}) : ORIGIN = 0x{region['base']:08X}, "
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f"LENGTH = 0x{region['size']:08X}"
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)
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lines += ["}", ""]
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return "\n".join(lines)
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def atomic_write(path: Path, content: str) -> None:
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path.parent.mkdir(parents=True, exist_ok=True)
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if path.exists() and path.read_text(encoding="utf-8") == content:
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return
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descriptor, temporary_name = tempfile.mkstemp(prefix=f".{path.name}.", dir=path.parent)
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try:
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with os.fdopen(descriptor, "w", encoding="utf-8", newline="\n") as output:
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output.write(content)
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os.replace(temporary_name, path)
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except BaseException:
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Path(temporary_name).unlink(missing_ok=True)
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raise
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def generate(map_path: Path, output_dir: Path, have_sram_if: str, ip: str) -> None:
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cpu_reset, regions = read_map(map_path)
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enabled_regions = [
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region for region in regions if region["requires_ip"] is None or region["requires_ip"] == ip
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]
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atomic_write(output_dir / "rtl" / "mmap_define.svh", render_rtl(cpu_reset, enabled_regions))
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atomic_write(output_dir / "memory_map.fl", f"+incdir+{output_dir / 'rtl'}\n")
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atomic_write(
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output_dir / "include" / "retrosoc" / "generated" / "memory_map.h",
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render_c(cpu_reset, enabled_regions, have_sram_if),
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)
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atomic_write(output_dir / "linker" / "memory_regions.ld", render_linker(enabled_regions))
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def main() -> int:
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parser = argparse.ArgumentParser(description=__doc__)
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parser.add_argument("--map", required=True, type=Path)
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parser.add_argument("--output-dir", type=Path)
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parser.add_argument("--have-sram-if", choices=("YES", "NO"), default="NO")
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parser.add_argument("--ip", choices=("NONE", "MDD"), default="NONE")
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parser.add_argument("--check", action="store_true", help="validate only; write nothing")
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arguments = parser.parse_args()
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try:
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if arguments.check:
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read_map(arguments.map)
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else:
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if arguments.output_dir is None:
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parser.error("--output-dir is required unless --check is used")
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generate(arguments.map, arguments.output_dir, arguments.have_sram_if, arguments.ip)
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except (OSError, ValueError, json.JSONDecodeError) as error:
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parser.error(str(error))
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return 0
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if __name__ == "__main__":
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raise SystemExit(main())
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