mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
410 lines
11 KiB
Systemverilog
410 lines
11 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`timescale 1 ns / 1 ps
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// `default_nettype none
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module retrosoc_tb;
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localparam real XTAL_CPU_FREQ = 24.0;
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localparam real EXT_CPU_FREQ = 72.0;
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localparam real AUD_CPU_FREQ = 18.432;
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integer sim_runtime;
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reg r_ext_clk;
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wire s_ext_clk;
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reg r_aud_clk;
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wire s_aud_clk;
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reg r_rst_n;
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wire s_rst_n;
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`ifdef HAVE_PLL
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reg r_xtal_clk;
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`endif
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reg [ 4:0] r_core_sel;
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wire [ 4:0] s_core_sel;
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wire s_user_gpio_0_io;
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reg r_user_gpio_0_io;
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wire s_uart0_tx;
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// for handle x-prop issue
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wire s_uart0_rx = 1'b1;
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wire s_gpio_0_io;
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wire s_gpio_1_ip;
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wire s_psram_sck;
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wire s_psram_nss0;
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wire s_psram_nss1;
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wire s_psram_dat0;
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wire s_psram_dat1;
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wire s_psram_dat2;
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wire s_psram_dat3;
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wire s_i2c0_sda_io;
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wire s_i2c0_scl_io;
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wire s_xpi_sck_o;
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wire s_xpi_nss0_o;
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wire s_xpi_nss1_o;
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wire s_xpi_nss2_o;
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wire s_xpi_dat0_io;
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wire s_xpi_dat1_io;
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wire s_xpi_dat2_io;
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wire s_xpi_dat3_io;
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wire s_i2s_sclk;
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wire s_i2s_lrck;
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wire s_i2s_adcdat;
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wire s_sdram_clk;
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wire s_sdram_cke;
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wire s_sdram_cs_n;
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wire s_sdram_ras_n;
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wire s_sdram_cas_n;
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wire s_sdram_we_n;
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wire [ 1:0] s_sdram_ba;
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wire [12:0] s_sdram_addr;
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wire [ 1:0] s_sdram_dqm;
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wire [15:0] s_sdram_dq;
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wire s_dvp_pclk;
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wire s_dvp_href;
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wire s_dvp_vsync;
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wire [ 7:0] s_dvp_data;
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wire s_uart1_tx;
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wire s_uart1_rx;
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wire s_ps2_clk;
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wire s_ps2_dat;
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`ifdef HAVE_PLL
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always #(1000 / XTAL_CPU_FREQ / 2) r_xtal_clk = (r_xtal_clk === 1'b0);
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`endif
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always #(1000 / EXT_CPU_FREQ / 2) r_ext_clk = (r_ext_clk === 1'b0);
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always #(1000 / AUD_CPU_FREQ / 2) r_aud_clk = (r_aud_clk === 1'b0);
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// connect inout pad
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assign s_ext_clk = r_ext_clk;
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assign s_aud_clk = r_aud_clk;
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assign s_rst_n = r_rst_n;
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assign s_core_sel = r_core_sel;
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assign s_user_gpio_0_io = r_user_gpio_0_io;
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retrosoc_asic u_retrosoc_asic (
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.extclk_i_pad (s_ext_clk),
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.audclk_i_pad (s_aud_clk),
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.ext_rst_n_i_pad (s_rst_n),
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`ifdef HAVE_PLL
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.xi_i_pad (r_xtal_clk),
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.xo_o_pad (),
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`endif
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`ifdef CORE_MDD
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.core_sel_0_i_pad (s_core_sel[0]),
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.core_sel_1_i_pad (s_core_sel[1]),
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.core_sel_2_i_pad (s_core_sel[2]),
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.core_sel_3_i_pad (s_core_sel[3]),
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.core_sel_4_i_pad (s_core_sel[4]),
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`endif
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`ifdef IP_MDD
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.user_gpio_0_io_pad (s_user_gpio_0_io),
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.user_gpio_1_io_pad (),
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.user_gpio_2_io_pad (),
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.user_gpio_3_io_pad (),
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.user_gpio_4_io_pad (),
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.user_gpio_5_io_pad (),
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.user_gpio_6_io_pad (),
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.user_gpio_7_io_pad (),
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.user_gpio_8_io_pad (),
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.user_gpio_9_io_pad (),
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.user_gpio_10_io_pad(),
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.user_gpio_11_io_pad(),
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.user_gpio_12_io_pad(),
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.user_gpio_13_io_pad(),
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.user_gpio_14_io_pad(),
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.user_gpio_15_io_pad(),
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`endif
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.gpio_0_io_pad (s_gpio_0_io),
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.gpio_1_io_pad (s_gpio_1_io),
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.gpio_2_io_pad (),
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.gpio_3_io_pad (),
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.gpio_4_io_pad (),
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.gpio_5_io_pad (),
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.gpio_6_io_pad (),
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.gpio_7_io_pad (s_i2c0_scl_io),
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.gpio_8_io_pad (s_i2c0_sda_io),
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.gpio_9_io_pad (),
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.gpio_10_io_pad (),
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.gpio_11_io_pad (),
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.gpio_12_io_pad (),
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.gpio_13_io_pad (),
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.gpio_14_io_pad (),
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.gpio_15_io_pad (),
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.gpio_16_io_pad (),
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.gpio_17_io_pad (),
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.gpio_18_io_pad (),
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.gpio_19_io_pad (),
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.gpio_20_io_pad (),
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.gpio_21_io_pad (s_psram_sck),
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.gpio_22_io_pad (s_psram_nss0),
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.gpio_23_io_pad (s_psram_dat0),
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.gpio_24_io_pad (s_psram_dat1),
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.gpio_25_io_pad (s_psram_dat2),
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.gpio_26_io_pad (s_psram_dat3),
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.gpio_27_io_pad (s_psram_nss1),
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.gpio_28_io_pad (),
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.gpio_29_io_pad (),
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.gpio_30_io_pad (),
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.gpio_31_io_pad (),
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.uart0_tx_o_pad (s_uart0_tx),
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.uart0_rx_i_pad (s_uart0_rx),
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.xpi_sck_o_pad (s_xpi_sck_o),
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.xpi_nss0_o_pad (s_xpi_nss0_o), // xpi flash
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.xpi_nss1_o_pad (s_xpi_nss1_o), // qpi flash
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.xpi_nss2_o_pad (s_xpi_nss2_o),
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.xpi_nss3_o_pad (), // tft test
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.xpi_dat0_io_pad (s_xpi_dat0_io),
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.xpi_dat1_io_pad (s_xpi_dat1_io),
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.xpi_dat2_io_pad (s_xpi_dat2_io),
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.xpi_dat3_io_pad (s_xpi_dat3_io),
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.sdram_clk_o_pad (s_sdram_clk),
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.sdram_cke_o_pad (s_sdram_cke),
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.sdram_cs_n_o_pad (s_sdram_cs_n),
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.sdram_ras_n_o_pad (s_sdram_ras_n),
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.sdram_cas_n_o_pad (s_sdram_cas_n),
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.sdram_we_n_o_pad (s_sdram_we_n),
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.sdram_ba0_o_pad (s_sdram_ba[0]),
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.sdram_ba1_o_pad (s_sdram_ba[1]),
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.sdram_addr0_o_pad (s_sdram_addr[0]),
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.sdram_addr1_o_pad (s_sdram_addr[1]),
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.sdram_addr2_o_pad (s_sdram_addr[2]),
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.sdram_addr3_o_pad (s_sdram_addr[3]),
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.sdram_addr4_o_pad (s_sdram_addr[4]),
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.sdram_addr5_o_pad (s_sdram_addr[5]),
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.sdram_addr6_o_pad (s_sdram_addr[6]),
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.sdram_addr7_o_pad (s_sdram_addr[7]),
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.sdram_addr8_o_pad (s_sdram_addr[8]),
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.sdram_addr9_o_pad (s_sdram_addr[9]),
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.sdram_addr10_o_pad (s_sdram_addr[10]),
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.sdram_addr11_o_pad (s_sdram_addr[11]),
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.sdram_addr12_o_pad (s_sdram_addr[12]),
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.sdram_dqm0_o_pad (s_sdram_dqm[0]),
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.sdram_dqm1_o_pad (s_sdram_dqm[1]),
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.sdram_dq0_io_pad (s_sdram_dq[0]),
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.sdram_dq1_io_pad (s_sdram_dq[1]),
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.sdram_dq2_io_pad (s_sdram_dq[2]),
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.sdram_dq3_io_pad (s_sdram_dq[3]),
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.sdram_dq4_io_pad (s_sdram_dq[4]),
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.sdram_dq5_io_pad (s_sdram_dq[5]),
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.sdram_dq6_io_pad (s_sdram_dq[6]),
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.sdram_dq7_io_pad (s_sdram_dq[7]),
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.sdram_dq8_io_pad (s_sdram_dq[8]),
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.sdram_dq9_io_pad (s_sdram_dq[9]),
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.sdram_dq10_io_pad (s_sdram_dq[10]),
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.sdram_dq11_io_pad (s_sdram_dq[11]),
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.sdram_dq12_io_pad (s_sdram_dq[12]),
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.sdram_dq13_io_pad (s_sdram_dq[13]),
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.sdram_dq14_io_pad (s_sdram_dq[14]),
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.sdram_dq15_io_pad (s_sdram_dq[15])
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);
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W25Q128JVxIM u_W25Q128JVxIM_norflash (
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.CSn (s_xpi_nss0_o),
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.CLK (s_xpi_sck_o),
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.DIO (s_xpi_dat0_io),
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.DO (s_xpi_dat1_io),
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.WPn (s_xpi_dat2_io),
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.HOLDn(s_xpi_dat3_io)
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);
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W25Q128JVxIM u_W25Q128JVxIM_1 (
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.CSn (s_xpi_nss1_o),
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.CLK (s_xpi_sck_o),
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.DIO (s_xpi_dat0_io),
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.DO (s_xpi_dat1_io),
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.WPn (s_xpi_dat2_io),
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.HOLDn(s_xpi_dat3_io)
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);
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sdr u_sdr (
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.Clk (s_sdram_clk),
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.Cke (s_sdram_cke),
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.Cs_n (s_sdram_cs_n),
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.Ras_n(s_sdram_ras_n),
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.Cas_n(s_sdram_cas_n),
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.We_n (s_sdram_we_n),
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.Addr (s_sdram_addr),
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.Ba (s_sdram_ba),
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.Dq (s_sdram_dq),
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.Dqm (s_sdram_dqm)
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);
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pullup u_i2c0_scl_pullup (s_i2c0_scl_io);
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pullup u_i2c0_sda_pullup (s_i2c0_sda_io);
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AT24C04 u_AT24C04_0 (
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.WP (1'b0),
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.SCL(s_i2c0_scl_io),
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.SDA(s_i2c0_sda_io)
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);
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rs232 #(
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.BAUD_RATE(921600)
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) u_rs232_0 (
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.rs232_rx_i(s_uart0_tx),
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.rs232_tx_o()
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);
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rs232 #(
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.BAUD_RATE(115200)
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) u_rs232_1 (
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.rs232_rx_i(s_uart1_tx),
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.rs232_tx_o(s_uart1_rx)
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);
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kdb_model u_kdb_model_0 (
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.ps2_clk_o(s_gpio_0_io),
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.ps2_dat_o(s_gpio_1_io)
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);
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kdb_model u_kdb_model_1 (
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.ps2_clk_o(s_ps2_clk),
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.ps2_dat_o(s_ps2_dat)
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);
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pullup u_psram_nss0_pullup (s_psram_nss0);
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ESP_PSRAM64H #(0) u_ESP_PSRAM64H_0 (
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.sclk(s_psram_sck),
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.csn (s_psram_nss0),
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.sio ({s_psram_dat3, s_psram_dat2, s_psram_dat1, s_psram_dat0})
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);
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pullup u_psram_nss1_pullup (s_psram_nss1);
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ESP_PSRAM64H #(1) u_ESP_PSRAM64H_1 (
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.sclk(s_psram_sck),
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.csn (s_psram_nss1),
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.sio ({s_psram_dat3, s_psram_dat2, s_psram_dat1, s_psram_dat0})
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);
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mic #(16) u_mic (
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.sck_i(s_i2s_sclk),
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.ws_i (s_i2s_lrck),
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.sd_o (s_i2s_adcdat)
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);
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DVP_CAMERA u_DVP_CAMERA (
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.pclk (s_dvp_pclk),
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.href (s_dvp_href),
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.vsync(s_dvp_vsync),
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.data (s_dvp_data)
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);
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initial begin
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r_rst_n = 1;
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#43;
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r_rst_n = 0;
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#170701;
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r_rst_n = 1;
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end
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initial begin : KDB_MODEL_0_BLOCK
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integer i;
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#1000;
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while (1) begin
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#1000;
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for (i = 0; i < 26; ++i) begin
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u_kdb_model_0.send_code(i + 8'd65);
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#500;
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end
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end
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end
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initial begin : KDB_MODEL_1_BLOCK
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integer i;
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#1000;
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while (1) begin
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#1000;
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for (i = 0; i < 26; ++i) begin
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u_kdb_model_1.send_code(i + 8'd65);
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#500;
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end
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end
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end
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initial begin : UART_RX_BLOCK
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integer i;
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#1000;
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while (1) begin
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#1000;
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for (i = 0; i < 26; ++i) begin
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u_rs232_1.send(i + 8'd66);
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#500;
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end
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end
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end
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initial begin : USER_GPIO_BLOCK
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integer i;
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#1000;
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r_user_gpio_0_io = 1'b0;
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while (1) begin
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#150000;
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r_user_gpio_0_io = ~r_user_gpio_0_io;
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end
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end
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initial begin
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if ($test$plusargs("wave_YES")) begin
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$display("== generate simulation wave ==");
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`ifdef SIMU_VCS
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$fsdbDumpfile("retrosoc_tb.fsdb");
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$fsdbDumpvars(0);
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$fsdbDumpMDA();
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`elsif SIMU_IVERILOG
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$dumpfile("retrosoc_tb.fst");
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$dumpvars(0);
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`endif
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#4705000;
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$finish;
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end
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end
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initial begin
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// sim_runtime = -1;
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// check for +TIMEOUT=xxx in the command line
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if ($value$plusargs("sim_timeout=%d", sim_runtime)) begin
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$display("Simulation timeout set to: %0dns", sim_runtime);
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end
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#sim_runtime;
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$display("Simulation reached timeout. Finishing...");
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$finish;
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end
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initial begin
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$display("========================================================");
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`ifdef CORE_MDD
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if (!$value$plusargs("core_sel=%d", r_core_sel)) r_core_sel = 5'd0;
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$display("core_sel: %0d", r_core_sel);
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`endif
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`ifdef HAVE_PLL
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$display("pll clock control: sysctrl");
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`else
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$display("ext clk_freq: %0dMHz", EXT_CPU_FREQ);
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`endif
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$display("========================================================");
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end
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endmodule
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