mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
50 lines
1.5 KiB
Plaintext
50 lines
1.5 KiB
Plaintext
/ip/native/memory/psram_core.sv
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/ip/native/memory/psram.sv
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/ip/native/memory/opipsram.sv
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/ip/native/memory/opipsram_core.sv
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/ip/native/storage/spisd_init.sv
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/ip/native/storage/spisd_read.sv
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/ip/native/storage/spisd_write.sv
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/ip/native/storage/spisd_reg.sv
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/ip/native/storage/spisd_cache.sv
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/ip/native/storage/spisd_core.sv
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/ip/native/storage/spisd_data.sv
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/ip/native/storage/spisd.sv
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/ip/native/storage/sdio.sv
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/ip/native/serial/i2c_core.sv
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/ip/native/serial/i2c.sv
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/ip/native/serial/i2s_reg.sv
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/ip/native/serial/i2s_clkgen.sv
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/ip/native/serial/i2s_recv.sv
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/ip/native/serial/i2s_send.sv
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/ip/native/serial/i2s_core.sv
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/ip/native/serial/i2s.sv
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/ip/native/serial/onewire_core.sv
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/ip/native/serial/onewire.sv
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/ip/native/storage/xpi_reg.sv
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/ip/native/storage/xpi_mm.sv
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/ip/native/storage/xpi_clkgen.sv
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/ip/native/storage/xpi_core.sv
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/ip/native/storage/xpi.sv
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/ip/native/peripheral/dma_core.sv
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/ip/native/peripheral/dma.sv
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/ip/native/peripheral/pll_ctrl_if.sv
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/ip/native/peripheral/sysctrl.sv
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/ip/native/peripheral/clint.sv
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/ip/native/memory/sdram_clkgen.sv
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/ip/native/memory/sdram_reg.sv
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/ip/native/memory/sdram_core.sv
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/ip/native/memory/sdram.sv
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/ip/native/multimedia/dvp_core.sv
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/ip/native/multimedia/dvp.sv
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/ip/native/peripheral/timer.sv
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/ip/native/serial/uart.sv
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/ip/native/peripheral/gpio.sv
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/ip/native/interconnect/nmi2apb.sv
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/ip/native/interconnect/ahbl2nmi.sv
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/ip/native/interconnect/axi4l2nmi.sv
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/ip/native/util/async_fifo.sv
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/ip/native/util/fifo.sv
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/ip/native/interconnect/nmi_regslice.sv
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/ip/native/interconnect/nmi2nmi.sv
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