mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
132 lines
6.0 KiB
Makefile
132 lines
6.0 KiB
Makefile
IVERILOG ?= iverilog
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VVP ?= vvp
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GTKWAVE ?= gtkwave
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NETLIST_PATH ?= $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v
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POST_PATH ?= $(ROOT_PATH)/pd/sdf/retrosoc_asic.v
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SDF_PATH ?= $(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz
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SDF_SCOPE ?= $(RTL_TOP).u_retrosoc_asic
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IVERILOG_ROOT := $(SIM_BUILD_ROOT)
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IVERILOG_BEHV_DIR := $(IVERILOG_ROOT)/behv
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IVERILOG_NETL_DIR := $(IVERILOG_ROOT)/netl
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IVERILOG_POST_DIR := $(IVERILOG_ROOT)/post
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IVERILOG_BEHV_FLIST := $(IVERILOG_BEHV_DIR)/iverilog.fl
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IVERILOG_NETL_FLIST := $(IVERILOG_NETL_DIR)/iverilog.fl
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IVERILOG_POST_FLIST := $(IVERILOG_POST_DIR)/iverilog.fl
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CONVERTED_SOC := $(IVERILOG_BEHV_DIR)/converted_soc.v
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CONVERTED_DEPFILE := $(IVERILOG_BEHV_DIR)/converted_soc.d
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IVERILOG_BEHV_SIMV := $(IVERILOG_BEHV_DIR)/simv
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IVERILOG_NETL_SIMV := $(IVERILOG_NETL_DIR)/simv
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IVERILOG_POST_SIMV := $(IVERILOG_POST_DIR)/simv
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IVERILOG_BEHV_DEPFILE := $(IVERILOG_BEHV_DIR)/simv.d
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IVERILOG_NETL_DEPFILE := $(IVERILOG_NETL_DIR)/simv.d
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IVERILOG_POST_DEPFILE := $(IVERILOG_POST_DIR)/simv.d
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-include $(CONVERTED_DEPFILE) $(IVERILOG_BEHV_DEPFILE) $(IVERILOG_NETL_DEPFILE) $(IVERILOG_POST_DEPFILE)
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IVERILOG_COMMON_OPTS := -g2012
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IVERILOG_TIME_OPTS := -gno-specify
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IVERILOG_POST_OPTS := -gspecify -Tmin
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IVERILOG_SIM_OPTS := +core_sel=$(RTL_SIM_CORESEL) +sim_timeout=$(RTL_SIM_TIMEOUT) +wave_$(WAVE)
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$(CONVERTED_SOC): $(MPW_VARIANT_STAMP) $(FILELIST_STAMP)
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@mkdir -p $(@D)
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python3 $(RTL_PATH)/script/convt_sv2v.py $(RTL_FLIST) --output $@
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python3 $(RTL_PATH)/script/filelist_deps.py $(RTL_FLIST) --target $@ \
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--output $(CONVERTED_DEPFILE)
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$(IVERILOG_BEHV_FLIST): $(FILELIST_STAMP) $(CONVERTED_SOC)
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@mkdir -p $(@D)
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python3 $(RTL_PATH)/script/gen_iverilog_filelist.py \
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--mode behv --pdk $(PDK) --generated-dir $(GENERATED_FL_DIR) \
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--output $@ --converted $(CONVERTED_SOC)
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$(IVERILOG_NETL_FLIST): $(FILELIST_STAMP) $(NETLIST_PATH)
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@mkdir -p $(@D)
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python3 $(RTL_PATH)/script/gen_iverilog_filelist.py \
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--mode netl --pdk $(PDK) --generated-dir $(GENERATED_FL_DIR) \
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--output $@ --netlist $(NETLIST_PATH)
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$(IVERILOG_POST_FLIST): $(FILELIST_STAMP) $(POST_PATH) $(SDF_PATH)
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@mkdir -p $(@D)
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python3 $(RTL_PATH)/script/gen_iverilog_filelist.py \
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--mode post --pdk $(PDK) --generated-dir $(GENERATED_FL_DIR) \
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--output $@ --netlist $(POST_PATH) --sdf $(SDF_PATH) \
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--sdf-scope $(SDF_SCOPE)
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convt_sv2v: $(CONVERTED_SOC)
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gen_iverilog_filelist: $(IVERILOG_BEHV_FLIST)
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$(IVERILOG_BEHV_SIMV): $(IVERILOG_BEHV_FLIST)
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@mkdir -p $(IVERILOG_BEHV_DIR)
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool iverilog \
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--log $(IVERILOG_BEHV_DIR)/compile.log --result $(IVERILOG_BEHV_DIR)/result-compile.json \
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--cwd $(IVERILOG_BEHV_DIR) -- $(IVERILOG) $(IVERILOG_COMMON_OPTS) \
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$(IVERILOG_TIME_OPTS) -f $< -o simv -s $(RTL_TOP)
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python3 $(RTL_PATH)/script/filelist_deps.py -f $(IVERILOG_BEHV_FLIST) \
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--target $@ --output $(IVERILOG_BEHV_DEPFILE)
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$(IVERILOG_NETL_SIMV): $(IVERILOG_NETL_FLIST)
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@mkdir -p $(IVERILOG_NETL_DIR)
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool iverilog \
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--log $(IVERILOG_NETL_DIR)/compile.log --result $(IVERILOG_NETL_DIR)/result-compile.json \
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--cwd $(IVERILOG_NETL_DIR) -- $(IVERILOG) $(IVERILOG_COMMON_OPTS) \
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$(IVERILOG_TIME_OPTS) -f $< -o simv -s $(RTL_TOP)
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python3 $(RTL_PATH)/script/filelist_deps.py -f $(IVERILOG_NETL_FLIST) \
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--target $@ --output $(IVERILOG_NETL_DEPFILE)
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$(IVERILOG_POST_SIMV): $(IVERILOG_POST_FLIST)
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@mkdir -p $(IVERILOG_POST_DIR)
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool iverilog \
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--log $(IVERILOG_POST_DIR)/compile.log --result $(IVERILOG_POST_DIR)/result-compile.json \
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--cwd $(IVERILOG_POST_DIR) -- $(IVERILOG) $(IVERILOG_COMMON_OPTS) \
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$(IVERILOG_POST_OPTS) -f $< -o simv -s $(RTL_TOP) -s retrosoc_sdf_annotator
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python3 $(RTL_PATH)/script/filelist_deps.py -f $(IVERILOG_POST_FLIST) \
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--target $@ --output $(IVERILOG_POST_DEPFILE)
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comp: $(IVERILOG_BEHV_SIMV)
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netcomp: $(IVERILOG_NETL_SIMV)
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postcomp: $(IVERILOG_POST_SIMV)
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sim: comp
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python3 $(RTL_PATH)/script/prepare_norflash.py --sim-dir $(IVERILOG_BEHV_DIR) \
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--firmware $(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).hex
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool iverilog-sim \
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--log $(IVERILOG_BEHV_DIR)/sim.log --result $(IVERILOG_BEHV_DIR)/result-sim.json \
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--cwd $(IVERILOG_BEHV_DIR) -- stdbuf -oL -eL $(VVP) simv -fst $(IVERILOG_SIM_OPTS)
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python3 $(ROOT_PATH)/scripts/check_simulation.py --log $(IVERILOG_BEHV_DIR)/sim.log \
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--result $(IVERILOG_BEHV_DIR)/result-sim-check.json --require '$(SIM_SUCCESS_MARKER)'
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netsim: netcomp
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python3 $(RTL_PATH)/script/prepare_norflash.py --sim-dir $(IVERILOG_NETL_DIR) \
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--firmware $(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).hex
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool iverilog-sim \
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--log $(IVERILOG_NETL_DIR)/sim.log --result $(IVERILOG_NETL_DIR)/result-sim.json \
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--cwd $(IVERILOG_NETL_DIR) -- stdbuf -oL -eL $(VVP) simv -fst $(IVERILOG_SIM_OPTS)
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python3 $(ROOT_PATH)/scripts/check_simulation.py --log $(IVERILOG_NETL_DIR)/sim.log \
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--result $(IVERILOG_NETL_DIR)/result-sim-check.json --require '$(SIM_SUCCESS_MARKER)'
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postsim: postcomp
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python3 $(RTL_PATH)/script/prepare_norflash.py --sim-dir $(IVERILOG_POST_DIR) \
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--firmware $(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).hex
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool iverilog-sim \
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--log $(IVERILOG_POST_DIR)/sim.log --result $(IVERILOG_POST_DIR)/result-sim.json \
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--cwd $(IVERILOG_POST_DIR) -- stdbuf -oL -eL $(VVP) simv -fst $(IVERILOG_SIM_OPTS)
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python3 $(ROOT_PATH)/scripts/check_simulation.py --log $(IVERILOG_POST_DIR)/sim.log \
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--result $(IVERILOG_POST_DIR)/result-sim-check.json --require '$(SIM_SUCCESS_MARKER)'
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comp netcomp postcomp sim netsim postsim: | manifest
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wave:
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cd $(IVERILOG_BEHV_DIR) && $(GTKWAVE) $(RTL_TOP).fst &
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netwave:
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cd $(IVERILOG_NETL_DIR) && $(GTKWAVE) $(RTL_TOP).fst &
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postwave:
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cd $(IVERILOG_POST_DIR) && $(GTKWAVE) $(RTL_TOP).fst &
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clean:
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python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(IVERILOG_ROOT)
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.PHONY: convt_sv2v gen_iverilog_filelist comp netcomp postcomp sim netsim postsim wave netwave postwave clean
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