mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
125 lines
5.1 KiB
Makefile
125 lines
5.1 KiB
Makefile
# tools & paths
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NOVAS ?= /nfs/tools/synopsys/verdi/V-2023.12-SP1-1/share/PLI/VCS/LINUX64
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VCS_RUNNER ?= bsub -Is
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VCS ?= vcs
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VERDI ?= verdi
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EXTRA ?= -P $(NOVAS)/novas.tab $(NOVAS)/pli.a
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SIM_TOOL := $(VCS_RUNNER) $(VCS)
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SIM_BINY := $(VCS_RUNNER) ./simv
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VERDI_TOOL := $(VCS_RUNNER) $(VERDI)
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COMP_LOG := -l compile.log
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SIM_LOG := -l sim.log
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# netlist file path
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NETLIST_PATH := -v $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v
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POST_PATH := -v $(ROOT_PATH)/pd/sdf/retrosoc_asic.v
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SDF_PATH := "$(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz"
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# testbench filelist
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TB_FLIST := -f $(GENERATED_FL_DIR)/tb.fl
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## vcs option
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# -debug_region=cell+lib
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# +lint=TFIPC-H(Timing, Floating Port, Implicit Net Declaration, Parameter, Comparison, High-Level)
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# +ling=PCWM-H(Port, Parameter, Unused Wire, Module Instantiation, High-Level)
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# -error=all(turn all warning into error)
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# +vcs+loopreport+100000 \
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# --- Compilation Flags ---
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COMMON_OPTS := -full64 +v2k -sverilog -timescale=1ns/10ps \
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$(EXTRA) \
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-kdb \
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-debug_access+all \
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-msg_config=$(GENERATED_FL_DIR)/lint.msg \
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+error+500 \
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+vcs+flush+all \
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-xprop=$(RTL_PATH)/xprop_config \
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-override_timescale=1ns/1ps \
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-reportstats \
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-work DEFAULT
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POST_OPTS := -sdf min:retrosoc_tb.u_retrosoc_asic:$(SDF_PATH) \
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+delay_mode_path \
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+sdfverbose \
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+neg_tchk \
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-negdelay \
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+optconfigfile+$(RTL_PATH)/disable_timing_checklist \
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-diag=sdf:verbose \
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+warn=OPD:10,IWNF:10,SDFCOM_UHICD:10,SDFCOM_ANICD:10,SDFCOM_NICD:10,DRTZ:10,SDFCOM_UHICD:10,SDFCOM_NTCDTL:10
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TIME_OPTION := +notimingcheck +nospecify
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SIM_OPTS := +vcs+loopreport+1000 -suppress=ASLR_DETECTED_INFO \
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+core_sel=$(RTL_SIM_CORESEL) +sim_timeout=$(RTL_SIM_TIMEOUT) +wave_$(WAVE)
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VCS_BEHV_DIR := $(SIM_BUILD_ROOT)/behv
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VCS_NETL_DIR := $(SIM_BUILD_ROOT)/netl
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VCS_POST_DIR := $(SIM_BUILD_ROOT)/post
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VCS_BEHV_SIMV := $(VCS_BEHV_DIR)/simv
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VCS_NETL_SIMV := $(VCS_NETL_DIR)/simv
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VCS_POST_SIMV := $(VCS_POST_DIR)/simv
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VCS_BEHV_DEPFILE := $(VCS_BEHV_DIR)/simv.d
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VCS_NETL_DEPFILE := $(VCS_NETL_DIR)/simv.d
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VCS_POST_DEPFILE := $(VCS_POST_DIR)/simv.d
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-include $(VCS_BEHV_DEPFILE) $(VCS_NETL_DEPFILE) $(VCS_POST_DEPFILE)
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$(VCS_BEHV_SIMV): DIR := $(VCS_BEHV_DIR)
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$(VCS_BEHV_SIMV): FLIST := $(RTL_FLIST) $(TB_FLIST)
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$(VCS_BEHV_SIMV): OPTS := $(TIME_OPTION)
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$(VCS_BEHV_SIMV): DEPFILE := $(VCS_BEHV_DEPFILE)
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$(VCS_BEHV_SIMV): DEPS_ARGS := $(RTL_FLIST) -f $(GENERATED_FL_DIR)/tb.fl
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$(VCS_NETL_SIMV): DIR := $(VCS_NETL_DIR)
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$(VCS_NETL_SIMV): FLIST := $(NETLIST_PATH) $(NET_FLIST) $(TB_FLIST)
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$(VCS_NETL_SIMV): OPTS := $(TIME_OPTION)
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$(VCS_NETL_SIMV): DEPFILE := $(VCS_NETL_DEPFILE)
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$(VCS_NETL_SIMV): DEPS_ARGS := $(NET_FLIST) -f $(GENERATED_FL_DIR)/tb.fl --extra $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v
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$(VCS_POST_SIMV): DIR := $(VCS_POST_DIR)
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$(VCS_POST_SIMV): FLIST := $(POST_PATH) $(NET_FLIST) $(TB_FLIST)
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$(VCS_POST_SIMV): OPTS := $(POST_OPTS)
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$(VCS_POST_SIMV): DEPFILE := $(VCS_POST_DEPFILE)
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$(VCS_POST_SIMV): DEPS_ARGS := $(NET_FLIST) -f $(GENERATED_FL_DIR)/tb.fl --extra $(ROOT_PATH)/pd/sdf/retrosoc_asic.v --extra $(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz
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sim: DIR := $(VCS_BEHV_DIR)
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netsim: DIR := $(VCS_NETL_DIR)
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postsim: DIR := $(VCS_POST_DIR)
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wave: DIR := $(SIM_BUILD_ROOT)/behv
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netwave: DIR := $(SIM_BUILD_ROOT)/netl
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postwave: DIR := $(SIM_BUILD_ROOT)/post
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comp: $(VCS_BEHV_SIMV)
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netcomp: $(VCS_NETL_SIMV)
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postcomp: $(VCS_POST_SIMV)
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sim: $(VCS_BEHV_SIMV)
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netsim: $(VCS_NETL_SIMV)
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postsim: $(VCS_POST_SIMV)
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$(VCS_BEHV_SIMV) $(VCS_NETL_SIMV) $(VCS_POST_SIMV): $(MPW_VARIANT_STAMP) $(FILELIST_STAMP)
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@mkdir -p $(DIR)
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool vcs --log $(DIR)/driver-compile.log \
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--result $(DIR)/result-compile.json --cwd $(DIR) -- \
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$(SIM_TOOL) $(COMMON_OPTS) $(OPTS) $(FLIST) -top $(RTL_TOP) $(COMP_LOG)
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python3 $(RTL_PATH)/script/filelist_deps.py $(DEPS_ARGS) --target $@ --output $(DEPFILE)
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$(VCS_NETL_SIMV): $(SYN_BUILD_ROOT)/out/retrosoc_asic_yosys.v
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$(VCS_POST_SIMV): $(ROOT_PATH)/pd/sdf/retrosoc_asic.v $(ROOT_PATH)/pd/sdf/retrosoc_asic_CTS_MIN.sdf.gz
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sim netsim postsim:
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python3 $(RTL_PATH)/script/prepare_norflash.py --sim-dir $(DIR) \
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--firmware $(SW_BUILD_DIR)/$(SIM_FIRMWARE_NAME).hex
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python3 $(ROOT_PATH)/scripts/run_flow.py --tool vcs-sim --log $(DIR)/driver-sim.log \
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--result $(DIR)/result-sim.json --cwd $(DIR) -- \
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$(SIM_BINY) $(SIM_OPTS) $(if $(filter netsim postsim,$@),+bus_conflict_off) $(SIM_LOG)
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python3 $(ROOT_PATH)/scripts/check_simulation.py --log $(DIR)/driver-sim.log \
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--result $(DIR)/result-sim-check.json --require '$(SIM_SUCCESS_MARKER)'
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comp netcomp postcomp sim netsim postsim: | manifest
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wave netwave postwave:
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cd $(DIR) && ($(VERDI_TOOL) -ssf $(RTL_TOP).fsdb -nologo &)
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clean:
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python3 $(ROOT_PATH)/scripts/clean.py --root $(ROOT_PATH) --path $(SIM_BUILD_ROOT)
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.PHONY: comp netcomp postcomp sim netsim postsim wave clean
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