mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
438 lines
14 KiB
Systemverilog
438 lines
14 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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// addr range: [31:28]: 4'h1(reg), 4'h4(psram), 4'h5(spisd)
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`include "mmap_define.svh"
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module ip_nmi_wrapper (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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input logic clk_aud_i,
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input logic rst_aud_n_i,
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// natv if
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nmi_if.slave nmi,
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gpio_if.dut gpio,
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uart_if.dut uart,
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psram_if.dut psram,
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spi_if.dut spisd,
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i2c_if.dut i2c0,
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i2s_if.dut i2s,
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onewire_if.dut onewire,
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xpi_if.dut xpi,
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nmi_if.master dma_nmi,
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sysctrl_if.dut sysctrl,
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pll_ctrl_if.sysctrl pll_ctrl,
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sdram_if.dut sdram,
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dvp_if.dut dvp,
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sdio_if.dut sdio,
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opipsram_if.dut opipsram,
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i2c_if.dut i2c1,
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input logic fault_valid_i,
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input logic [31:0] fault_addr_i,
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input logic [3:0] fault_wstrb_i,
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input logic fault_reserved_i,
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// irq
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output logic [9:0] irq_o
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// verilog_format: on
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);
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// bus interface
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nmi_if u_uart_nmi_if ();
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nmi_if u_gpio_nmi_if ();
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nmi_if u_tim0_nmi_if ();
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nmi_if u_tim1_nmi_if ();
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nmi_if u_psram_nmi_if ();
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nmi_if u_spisd_nmi_if ();
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nmi_if u_i2c0_nmi_if ();
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nmi_if u_i2s_nmi_if ();
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nmi_if u_onewire_nmi_if ();
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nmi_if u_xpi_nmi_if ();
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nmi_if u_dma_nmi_if ();
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nmi_if u_sysctrl_nmi_if ();
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nmi_if u_clint_nmi_if ();
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nmi_if u_sdram_nmi_if ();
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nmi_if u_dvp_nmi_if ();
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nmi_if u_sdio_nmi_if ();
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nmi_if u_opipsram_nmi_if ();
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nmi_if u_i2c1_nmi_if ();
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// ip interface
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simp_clint_if u_clint_if ();
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dma_hw_trg_if u_dma_hw_trg_if ();
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// cfg or mem
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logic s_psram_cfg_sel, s_psram_mem_sel;
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logic s_opipsram_cfg_sel, s_opipsram_mem_sel;
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logic s_spisd_cfg_sel;
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logic s_sdram_cfg_sel, s_sdram_mem_sel;
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logic s_xpi_cfg_sel, s_xpi_mem_sel;
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// dma
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logic s_dma_i2s_tx_stall, s_dma_i2s_rx_stall;
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logic s_dma_xpi_tx_stall, s_dma_xpi_rx_stall;
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logic s_dma_xfer_done;
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// irq
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logic s_tim0_irq, s_tim1_irq;
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// dma channel
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assign u_dma_hw_trg_if.i2s_tx_proc = ~s_dma_i2s_tx_stall;
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assign u_dma_hw_trg_if.i2s_rx_proc = ~s_dma_i2s_rx_stall;
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assign u_dma_hw_trg_if.qspi_tx_proc = ~s_dma_xpi_tx_stall;
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assign u_dma_hw_trg_if.qspi_rx_proc = ~s_dma_xpi_rx_stall;
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// gpio
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assign u_gpio_nmi_if.valid = nmi.valid && `SOC_ADDR_IS_NMI_GPIO(nmi.addr);
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assign u_gpio_nmi_if.addr = nmi.addr;
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assign u_gpio_nmi_if.wdata = nmi.wdata;
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assign u_gpio_nmi_if.wstrb = nmi.wstrb;
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// uart
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assign u_uart_nmi_if.valid = nmi.valid && `SOC_ADDR_IS_NMI_UART0(nmi.addr);
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assign u_uart_nmi_if.addr = nmi.addr;
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assign u_uart_nmi_if.wdata = nmi.wdata;
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assign u_uart_nmi_if.wstrb = nmi.wstrb;
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// tim0
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assign u_tim0_nmi_if.valid = nmi.valid && `SOC_ADDR_IS_NMI_TIM0(nmi.addr);
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assign u_tim0_nmi_if.addr = nmi.addr;
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assign u_tim0_nmi_if.wdata = nmi.wdata;
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assign u_tim0_nmi_if.wstrb = nmi.wstrb;
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// tim1
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assign u_tim1_nmi_if.valid = nmi.valid && `SOC_ADDR_IS_NMI_TIM1(nmi.addr);
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assign u_tim1_nmi_if.addr = nmi.addr;
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assign u_tim1_nmi_if.wdata = nmi.wdata;
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assign u_tim1_nmi_if.wstrb = nmi.wstrb;
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// psram
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assign s_psram_cfg_sel = `SOC_ADDR_IS_NMI_PSRAM(nmi.addr);
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assign s_psram_mem_sel = `SOC_ADDR_IS_PSRAM(nmi.addr);
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assign u_psram_nmi_if.valid = nmi.valid && (s_psram_mem_sel || s_psram_cfg_sel);
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assign u_psram_nmi_if.addr = nmi.addr;
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assign u_psram_nmi_if.wdata = nmi.wdata;
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assign u_psram_nmi_if.wstrb = nmi.wstrb;
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// spisd
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assign s_spisd_cfg_sel = `SOC_ADDR_IS_NMI_SPISD(nmi.addr);
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assign u_spisd_nmi_if.valid = nmi.valid && (`SOC_ADDR_IS_SPISD(nmi.addr) || s_spisd_cfg_sel);
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assign u_spisd_nmi_if.addr = nmi.addr;
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assign u_spisd_nmi_if.wdata = nmi.wdata;
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assign u_spisd_nmi_if.wstrb = nmi.wstrb;
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// i2c0
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assign u_i2c0_nmi_if.valid = nmi.valid && `SOC_ADDR_IS_NMI_I2C0(nmi.addr);
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assign u_i2c0_nmi_if.addr = nmi.addr;
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assign u_i2c0_nmi_if.wdata = nmi.wdata;
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assign u_i2c0_nmi_if.wstrb = nmi.wstrb;
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// i2s
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assign u_i2s_nmi_if.valid = nmi.valid && `SOC_ADDR_IS_NMI_I2S(nmi.addr);
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assign u_i2s_nmi_if.addr = nmi.addr;
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assign u_i2s_nmi_if.wdata = nmi.wdata;
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assign u_i2s_nmi_if.wstrb = nmi.wstrb;
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// onewire
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assign u_onewire_nmi_if.valid = nmi.valid && `SOC_ADDR_IS_NMI_ONEWIRE(nmi.addr);
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assign u_onewire_nmi_if.addr = nmi.addr;
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assign u_onewire_nmi_if.wdata = nmi.wdata;
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assign u_onewire_nmi_if.wstrb = nmi.wstrb;
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// xpi
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assign s_xpi_cfg_sel = `SOC_ADDR_IS_NMI_XPI(nmi.addr);
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assign s_xpi_mem_sel = `SOC_ADDR_IS_FLASH(nmi.addr) || `SOC_ADDR_IS_XPI(nmi.addr);
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assign u_xpi_nmi_if.valid = nmi.valid && (s_xpi_cfg_sel || s_xpi_mem_sel);
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assign u_xpi_nmi_if.addr = nmi.addr;
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assign u_xpi_nmi_if.wdata = nmi.wdata;
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assign u_xpi_nmi_if.wstrb = nmi.wstrb;
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// dma
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assign u_dma_nmi_if.valid = nmi.valid && `SOC_ADDR_IS_NMI_DMA(nmi.addr);
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assign u_dma_nmi_if.addr = nmi.addr;
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assign u_dma_nmi_if.wdata = nmi.wdata;
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assign u_dma_nmi_if.wstrb = nmi.wstrb;
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// sysctrl
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assign u_sysctrl_nmi_if.valid = nmi.valid && `SOC_ADDR_IS_NMI_SYSCTRL(nmi.addr);
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assign u_sysctrl_nmi_if.addr = nmi.addr;
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assign u_sysctrl_nmi_if.wdata = nmi.wdata;
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assign u_sysctrl_nmi_if.wstrb = nmi.wstrb;
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// clint
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assign u_clint_nmi_if.valid = nmi.valid && `SOC_ADDR_IS_NMI_CLINT(nmi.addr);
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assign u_clint_nmi_if.addr = nmi.addr;
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assign u_clint_nmi_if.wdata = nmi.wdata;
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assign u_clint_nmi_if.wstrb = nmi.wstrb;
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// sdram
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assign s_sdram_cfg_sel = `SOC_ADDR_IS_NMI_SDRAM(nmi.addr);
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assign s_sdram_mem_sel = `SOC_ADDR_IS_SDRAM(nmi.addr);
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assign u_sdram_nmi_if.valid = nmi.valid && (s_sdram_cfg_sel || s_sdram_mem_sel);
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assign u_sdram_nmi_if.addr = nmi.addr;
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assign u_sdram_nmi_if.wdata = nmi.wdata;
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assign u_sdram_nmi_if.wstrb = nmi.wstrb;
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// dvp
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assign u_dvp_nmi_if.valid = nmi.valid && `SOC_ADDR_IS_NMI_DVP(nmi.addr);
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assign u_dvp_nmi_if.addr = nmi.addr;
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assign u_dvp_nmi_if.wdata = nmi.wdata;
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assign u_dvp_nmi_if.wstrb = nmi.wstrb;
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// sdio
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assign u_sdio_nmi_if.valid = 1'b0;
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assign u_sdio_nmi_if.addr = nmi.addr;
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assign u_sdio_nmi_if.wdata = nmi.wdata;
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assign u_sdio_nmi_if.wstrb = nmi.wstrb;
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// opipsram
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assign s_opipsram_cfg_sel = 1'b0;
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assign s_opipsram_mem_sel = 1'b0;
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assign u_opipsram_nmi_if.valid = 1'b0;
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assign u_opipsram_nmi_if.addr = nmi.addr;
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assign u_opipsram_nmi_if.wdata = nmi.wdata;
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assign u_opipsram_nmi_if.wstrb = nmi.wstrb;
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// i2c1
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assign u_i2c1_nmi_if.valid = nmi.valid && `SOC_ADDR_IS_NMI_I2C1(nmi.addr);
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assign u_i2c1_nmi_if.addr = nmi.addr;
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assign u_i2c1_nmi_if.wdata = nmi.wdata;
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assign u_i2c1_nmi_if.wstrb = nmi.wstrb;
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// verilog_format: off
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// Registered one-hot slave select for response mux (breaks comb fanin)
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logic [17:0] s_slv_sel_d, s_slv_sel_q;
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assign s_slv_sel_d = { u_i2c1_nmi_if.valid,
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u_opipsram_nmi_if.valid,
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u_sdio_nmi_if.valid,
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u_dvp_nmi_if.valid,
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u_sdram_nmi_if.valid,
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u_clint_nmi_if.valid,
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u_sysctrl_nmi_if.valid,
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u_dma_nmi_if.valid,
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u_xpi_nmi_if.valid,
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u_onewire_nmi_if.valid,
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u_i2s_nmi_if.valid,
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u_i2c0_nmi_if.valid,
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u_spisd_nmi_if.valid,
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u_psram_nmi_if.valid,
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u_tim1_nmi_if.valid,
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u_tim0_nmi_if.valid,
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u_gpio_nmi_if.valid,
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u_uart_nmi_if.valid };
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dffr #(18) u_slv_sel_dffr (
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clk_i,
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rst_n_i,
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s_slv_sel_d,
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s_slv_sel_q
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);
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// Collect per-slave ready signals into a vector
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logic [17:0] s_slv_ready;
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assign s_slv_ready = { u_i2c1_nmi_if.ready,
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u_opipsram_nmi_if.ready,
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u_sdio_nmi_if.ready,
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u_dvp_nmi_if.ready,
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u_sdram_nmi_if.ready,
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u_clint_nmi_if.ready,
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u_sysctrl_nmi_if.ready,
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u_dma_nmi_if.ready,
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u_xpi_nmi_if.ready,
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u_onewire_nmi_if.ready,
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u_i2s_nmi_if.ready,
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u_i2c0_nmi_if.ready,
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u_spisd_nmi_if.ready,
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u_psram_nmi_if.ready,
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u_tim1_nmi_if.ready,
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u_tim0_nmi_if.ready,
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u_gpio_nmi_if.ready,
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u_uart_nmi_if.ready };
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assign nmi.ready = |(s_slv_sel_q & s_slv_ready);
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// Registered select mux for rdata (reduces fanin from 18 to a clean one-hot mux)
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logic [31:0] s_slv_rdata [0:17];
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assign s_slv_rdata[0] = u_uart_nmi_if.rdata;
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assign s_slv_rdata[1] = u_gpio_nmi_if.rdata;
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assign s_slv_rdata[2] = u_tim0_nmi_if.rdata;
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assign s_slv_rdata[3] = u_tim1_nmi_if.rdata;
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assign s_slv_rdata[4] = u_psram_nmi_if.rdata;
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assign s_slv_rdata[5] = u_spisd_nmi_if.rdata;
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assign s_slv_rdata[6] = u_i2c0_nmi_if.rdata;
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assign s_slv_rdata[7] = u_i2s_nmi_if.rdata;
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assign s_slv_rdata[8] = u_onewire_nmi_if.rdata;
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assign s_slv_rdata[9] = u_xpi_nmi_if.rdata;
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assign s_slv_rdata[10] = u_dma_nmi_if.rdata;
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assign s_slv_rdata[11] = u_sysctrl_nmi_if.rdata;
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assign s_slv_rdata[12] = u_clint_nmi_if.rdata;
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assign s_slv_rdata[13] = u_sdram_nmi_if.rdata;
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assign s_slv_rdata[14] = u_dvp_nmi_if.rdata;
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assign s_slv_rdata[15] = u_sdio_nmi_if.rdata;
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assign s_slv_rdata[16] = u_opipsram_nmi_if.rdata;
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assign s_slv_rdata[17] = u_i2c1_nmi_if.rdata;
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// One-hot mux using registered slave select
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always_comb begin
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nmi.rdata = '0;
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for (int i = 0; i < 18; i++) begin
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if (s_slv_sel_q[i]) nmi.rdata = nmi.rdata | s_slv_rdata[i];
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end
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end
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// verilog_format: on
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// irq
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assign irq_o[0] = u_clint_if.sfr_irq_o;
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assign irq_o[1] = u_clint_if.tmr_irq_o;
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assign irq_o[2] = uart.irq_o;
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assign irq_o[3] = s_tim0_irq;
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assign irq_o[4] = s_tim1_irq;
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assign irq_o[5] = psram.irq_o;
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assign irq_o[6] = spisd.irq_o;
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assign irq_o[7] = i2c0.irq_o;
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assign irq_o[8] = i2s.irq_o;
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assign irq_o[9] = xpi.irq_o;
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nmi_gpio u_nmi_gpio (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.nmi (u_gpio_nmi_if),
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.gpio (gpio)
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);
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nmi_uart u_nmi_uart (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.nmi (u_uart_nmi_if),
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.uart (uart)
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);
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nmi_timer u_nmi_timer0 (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.nmi (u_tim0_nmi_if),
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.irq_o (s_tim0_irq)
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);
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nmi_timer u_nmi_timer1 (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.nmi (u_tim1_nmi_if),
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.irq_o (s_tim1_irq)
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);
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nmi_psram u_nmi_psram (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.nmi (u_psram_nmi_if),
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.psram (psram)
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);
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nmi_spisd u_nmi_spisd (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.nmi (u_spisd_nmi_if),
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.spi (spisd)
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);
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nmi_i2c u_nmi_i2c0 (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.nmi (u_i2c0_nmi_if),
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.i2c (i2c0)
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);
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nmi_i2s u_nmi_i2s (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clk_aud_i (clk_aud_i),
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.rst_aud_n_i (rst_aud_n_i),
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.dma_tx_stall_o(s_dma_i2s_tx_stall),
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.dma_rx_stall_o(s_dma_i2s_rx_stall),
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.nmi (u_i2s_nmi_if),
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.i2s (i2s)
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);
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nmi_onewire u_nmi_onewire (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.nmi (u_onewire_nmi_if),
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.onewire(onewire)
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);
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nmi_xpi u_nmi_xpi (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_xfer_done_i(s_dma_xfer_done),
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.dma_tx_stall_o (s_dma_xpi_tx_stall),
|
|
.dma_rx_stall_o (s_dma_xpi_rx_stall),
|
|
.nmi (u_xpi_nmi_if),
|
|
.xpi (xpi)
|
|
);
|
|
|
|
nmi_dma u_nmi_dma (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.dma_xfer_done_o(s_dma_xfer_done),
|
|
.hw_trg (u_dma_hw_trg_if),
|
|
.nmi (u_dma_nmi_if),
|
|
.nmi_dma (dma_nmi)
|
|
);
|
|
|
|
nmi_sysctrl u_nmi_sysctrl (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.fault_valid_i (fault_valid_i),
|
|
.fault_addr_i (fault_addr_i),
|
|
.fault_wstrb_i (fault_wstrb_i),
|
|
.fault_reserved_i(fault_reserved_i),
|
|
.nmi (u_sysctrl_nmi_if),
|
|
.sysctrl (sysctrl),
|
|
.pll_ctrl (pll_ctrl)
|
|
);
|
|
|
|
nmi_clint u_nmi_clint (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.nmi (u_clint_nmi_if),
|
|
.clint (u_clint_if)
|
|
);
|
|
|
|
|
|
nmi_sdram u_nmi_sdram (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.nmi (u_sdram_nmi_if),
|
|
.sdram (sdram)
|
|
);
|
|
|
|
|
|
nmi_dvp u_nmi_dvp (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.nmi (u_dvp_nmi_if),
|
|
.dvp (dvp)
|
|
);
|
|
|
|
|
|
nmi_sdio u_nmi_sdio (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.nmi (u_sdio_nmi_if),
|
|
.sdio (sdio)
|
|
);
|
|
|
|
|
|
nmi_opipsram u_nmi_opipsram (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.nmi (u_opipsram_nmi_if),
|
|
.psram (opipsram)
|
|
);
|
|
|
|
|
|
nmi_i2c u_nmi_i2c1 (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.nmi (u_i2c1_nmi_if),
|
|
.i2c (i2c1)
|
|
);
|
|
|
|
endmodule
|