mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
161 lines
3.4 KiB
Systemverilog
161 lines
3.4 KiB
Systemverilog
// Copyright 2023 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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// Authors:
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//
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// -Thomas Benz <tbenz@iis.ee.ethz.ch>
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// -Tobias Senti <tsenti@student.ethz.ch>
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//
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// -- Adaptable modifications are redistributed under compatible License --
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//
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// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module tc_clk_inv (
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input logic clk_i,
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output logic clk_o
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);
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`ifdef PDK_BEHAV
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assign clk_o = ~clk_i;
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`elsif PDK_IHP130
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(* keep *) (* dont_touch = "true" *)
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sg13g2_inv_1 u_sg13g2_inv_1 (
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.A(clk_i),
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.Y(clk_o)
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);
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`elsif PDK_S110
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(* keep *) (* dont_touch = "true" *)
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assign clk_o = ~clk_i; // HACK:
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`elsif PDK_ICS55
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(* keep *) (* dont_touch = "true" *)
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INVX0P5H7R u_INVX0P5H7R (
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.A(clk_i),
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.Y(clk_o)
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);
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`endif
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endmodule
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module tc_clk_buf (
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input logic clk_i,
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output logic clk_o
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);
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`ifdef PDK_BEHAV
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assign clk_o = clk_i;
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`elsif PDK_IHP130
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(* keep *) (* dont_touch = "true" *)
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sg13g2_buf_1 u_sg13g2_buf_1 (
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.A(clk_i),
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.X(clk_o)
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);
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`elsif PDK_S110
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(* keep *) (* dont_touch = "true" *)
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LVT_CLKBUFHDV12 u_LVT_CLKBUFHDV12 (
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.I(clk_i),
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.Z(clk_o)
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);
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`elsif PDK_ICS55
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(* keep *) (* dont_touch = "true" *)
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BUFX0P7H7R u_BUFX0P7H7R (
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.A(clk_i),
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.Y(clk_o)
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);
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`endif
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endmodule
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module tc_clk_mux2 (
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input logic clk0_i,
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input logic clk1_i,
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input logic clk_sel_i,
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output logic clk_o
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);
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`ifdef PDK_BEHAV
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assign clk_o = clk_sel_i ? clk1_i : clk0_i;
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`elsif PDK_IHP130
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(* keep *) (* dont_touch = "true" *)
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sg13g2_mux2_1 u_sg13g2_mux2_1 (
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.A0(clk0_i),
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.A1(clk1_i),
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.S (clk_sel_i),
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.X (clk_o)
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);
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`elsif PDK_S110
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(* keep *) (* dont_touch = "true" *)
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LVT_CKMUX2HDV4 u_LVT_CKMUX2HDV4 (
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.S (clk_sel_i),
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.I0(clk0_i),
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.I1(clk1_i),
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.Z (clk_o)
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);
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`elsif PDK_ICS55
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(* keep *) (* dont_touch = "true" *)
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MUX2X0P5H7R u_MUX2X0P5H7R (
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.S0(clk_sel_i),
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.A (clk0_i),
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.B (clk1_i),
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.Y (clk_o)
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);
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`endif
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endmodule
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// Dynamic clock switching is enabled only with the behavioral PLL backend.
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// Silicon backends keep capability low until this wrapper is replaced by a
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// characterized, glitch-free clock-switch cell.
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module tc_clk_switch2 (
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input logic clk0_i,
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input logic clk1_i,
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input logic clk_sel_i,
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output logic clk_o
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);
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`ifdef PDK_BEHAV
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assign clk_o = clk_sel_i ? clk1_i : clk0_i;
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`else
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tc_clk_mux2 u_tc_clk_mux2 (
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.clk0_i (clk0_i),
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.clk1_i (clk1_i),
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.clk_sel_i(clk_sel_i),
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.clk_o (clk_o)
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);
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`endif
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endmodule
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module tc_clk_xor2 (
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input logic clk0_i,
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input logic clk1_i,
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output logic clk_o
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);
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`ifdef PDK_BEHAV
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assign clk_o = clk0_i ^ clk1_i;
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`elsif PDK_IHP130
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(* keep *) (* dont_touch = "true" *)
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sg13g2_xor2_1 i_mux (
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.A(clk0_i),
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.B(clk1_i),
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.X(clk_o)
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);
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`endif
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endmodule
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