mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
124 lines
3.2 KiB
Systemverilog
124 lines
3.2 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module tc_pll (
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input logic fref_i,
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input logic rst_n_i,
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input logic [2:0] cfg_sel_i,
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input logic cfg_apply_i,
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output logic pll_capable_o,
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output logic pll_lock_o,
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output logic pll_clk_o
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);
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`ifdef PDK_BEHAV
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localparam logic [2:0] PLL_LOCK_CYCLES = 3'd4;
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logic [2:0] s_cfg_sel_d, s_cfg_sel_q;
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logic [2:0] s_lock_count_d, s_lock_count_q;
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logic s_lock_d, s_lock_q;
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logic s_apply_seen_d, s_apply_seen_q;
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logic s_cfg_apply;
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logic s_force_lock_fail;
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time s_last_ref_edge;
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time s_ref_period;
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function automatic int pll_multiplier(input logic [2:0] cfg_sel);
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case (cfg_sel)
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3'd0: pll_multiplier = 1;
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3'd1: pll_multiplier = 2;
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3'd2: pll_multiplier = 3;
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3'd3: pll_multiplier = 4;
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3'd4: pll_multiplier = 5;
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3'd5: pll_multiplier = 6;
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3'd6: pll_multiplier = 7;
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default: pll_multiplier = 8;
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endcase
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endfunction
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initial begin
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s_force_lock_fail = $test$plusargs("pll_lock_fail");
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s_last_ref_edge = 0;
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s_ref_period = 0;
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pll_clk_o = 1'b0;
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end
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always @(posedge fref_i) begin
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if (s_last_ref_edge != 0) begin
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s_ref_period = $time - s_last_ref_edge;
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end
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s_last_ref_edge = $time;
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end
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always begin
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@(posedge fref_i);
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wait (pll_lock_o);
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while (pll_lock_o) begin
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#(s_ref_period / (2 * pll_multiplier(s_cfg_sel_q)));
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if (pll_lock_o) begin
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pll_clk_o = ~pll_clk_o;
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end
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end
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pll_clk_o = 1'b0;
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end
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assign pll_capable_o = 1'b1;
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assign pll_lock_o = s_lock_q;
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assign s_cfg_apply = cfg_apply_i && !s_apply_seen_q;
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assign s_cfg_sel_d = cfg_sel_i;
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dffer #(3) u_cfg_sel_dffer (
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fref_i,
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rst_n_i,
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s_cfg_apply,
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s_cfg_sel_d,
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s_cfg_sel_q
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);
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assign s_apply_seen_d = cfg_apply_i;
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dffr #(1) u_apply_seen_dffr (
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fref_i,
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rst_n_i,
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s_apply_seen_d,
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s_apply_seen_q
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);
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always_comb begin
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s_lock_count_d = s_lock_count_q;
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s_lock_d = s_lock_q;
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if (s_cfg_apply) begin
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s_lock_count_d = '0;
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s_lock_d = 1'b0;
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end else if (!s_lock_q && !s_force_lock_fail) begin
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if (s_lock_count_q == PLL_LOCK_CYCLES - 1'b1) begin
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s_lock_d = 1'b1;
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end else begin
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s_lock_count_d = s_lock_count_q + 1'b1;
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end
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end
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end
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dffr #(3) u_lock_count_dffr (
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fref_i,
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rst_n_i,
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s_lock_count_d,
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s_lock_count_q
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);
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dffr #(1) u_lock_dffr (
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fref_i,
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rst_n_i,
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s_lock_d,
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s_lock_q
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);
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`else
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assign pll_capable_o = 1'b0;
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assign pll_lock_o = 1'b0;
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assign pll_clk_o = fref_i;
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`endif
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endmodule
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