mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
33 lines
1.4 KiB
Tcl
33 lines
1.4 KiB
Tcl
# Mini SoC default external-safe-clock timing mode.
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# Dynamic PLL timing modes are enabled only after a PDK backend supplies a
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# characterized PLL macro and a glitch-free switch cell.
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set clk_ext_freq 72.0
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set clk_aud_freq 18.432
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set clk_ext_period [expr 1000.0 / $clk_ext_freq]
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set clk_aud_period [expr 1000.0 / $clk_aud_freq]
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create_clock -name clk_ext -period $clk_ext_period [get_ports extclk_i_pad]
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create_clock -name clk_aud -period $clk_aud_period [get_ports audclk_i_pad]
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create_generated_clock -name clk_i2s_mclk_o -source [get_pins \u_rcu.u_aud_clk_buf/clk_o] \
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-divide_by 1 [get_ports gpio_10_io_pad]
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set_input_transition .1 [all_inputs]
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set_clock_uncertainty -setup 0.2 [get_clocks clk_ext]
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set_clock_uncertainty -hold 0.1 [get_clocks clk_ext]
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set_clock_uncertainty -setup 0.2 [get_clocks clk_aud]
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set_clock_uncertainty -hold 0.1 [get_clocks clk_aud]
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set_clock_uncertainty -setup 0.2 [get_clocks clk_i2s_mclk_o]
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set_clock_uncertainty -hold 0.1 [get_clocks clk_i2s_mclk_o]
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set_timing_derate -cell_delay -net_delay -late 1
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set_timing_derate -net_delay -clock -early 0.95
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set_timing_derate -net_delay -data -early 1
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set_timing_derate -cell_delay -clock -early 0.95
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set_timing_derate -cell_delay -data -early 1
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set_clock_groups -name cgp_async -asynchronous -group [get_clocks clk_ext] \
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-group [get_clocks clk_aud]
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set_false_path -from [get_cells \u_rcu.u_ext_rst_sync*]
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set_false_path -from [get_cells \u_rcu.u_aud_rst_sync*]
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