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maksyuki fc898bc4ab feat: add PLL controller and related testbench functionality

- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc.
- Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing.
- Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization.
- Enhanced memory map tests to verify PLL configuration and status offsets.
- Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.

2026-07-20 22:12:17 +08:00

refactor: refactor embedded C policy and enhance warning checks

2026-07-11 12:43:26 +08:00

rtl

feat: add PLL controller and related testbench functionality

2026-07-20 22:12:17 +08:00

README.md

feat: add README files for various directories to document structure and usage

2026-07-11 13:18:38 +08:00

test_memory_map.py

feat: add PLL controller and related testbench functionality

2026-07-20 22:12:17 +08:00

test_script_tools.py

feat: add QSPI Flash and Flash Read Binder modules

2026-07-20 16:50:57 +08:00

README.md

Repository Tests

This directory contains tests for deterministic SDK behavior and build/quality tooling.

c/test_runtime.c is the host C test program used by make sw-host-test.
test_script_tools.py covers setup, dependency, filelist, warning, metric, archive, and regression-helper behavior.

Add a host C test when changing deterministic runtime or media logic; add a Python test when changing scripts or build policy. Run:

make sw-host-test
python3 -m pytest -q

These tests complement, but do not replace, firmware builds, RTL simulation, synthesis, timing, or hardware validation.