Files
retroSoC/.gitignore
T

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*.log
*.hex
*.elf
*.o
*.flash
*.bin
*.vvp
*.vcd
*.lib
*.report
*.ddb
*.fst
*.txt
*.demo
!requirements/
!requirements/*.txt
*.gtkw
*.vmf
*.tar.bz2
*.tbsim
*.fsdb
*.conf
*.rc
*.aig
*.so
*.py[cod]
__pycache__/
.vscode
pic
video.h
image.h
audio_file.h
.generated_fl
.sw_build
.build
.net_build
.post_build
.synth_build
.vcs_build
.verilator_build
.iverilog_build
.metals
.mypy_cache
.pytest_cache
/build/
/.cache/
/dist/
.vscode
retrosoc_sections.lds
retrosoc_syn*
s110
icsprout55-pdk
IHP-Open-PDK
skywater-pdk
gf180mcu-pdk
demo*
dont_use_cell_*
nanoV
tinyQV
kianV
hazard3
def.fl
*yosys*.fl
*verilator*.fl
!rtl/filelist/pdk_ics55_yosys.fl
!rtl/filelist/pdk_ics55_verilator.fl
minirv.sv
user_design
*.zip
*.tar*
ff16
lvgl-*
coremark-main
*wave
socver.*
/rtl/managed/clusterip/*
!/rtl/managed/clusterip/setup.py
/rtl/managed/mpw/
/rtl/managed/third_party/
*result.json