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chore: add timer if into a single file
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@@ -8,12 +8,7 @@
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "register.sv"
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`include "clk_int_div.sv"
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`include "cdc_sync.sv"
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`include "counter.sv"
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`include "edge_det.sv"
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`include "tmr_define.sv"
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`include "tmr_define.svh"
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module apb4_tmr (
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apb4_if.slave apb4,
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@@ -70,13 +70,4 @@
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`define TMR_ETM_LOAD 3'b100
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// verilog_format: on
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interface tmr_if (
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input logic exclk_i
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);
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logic capch_i;
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logic irq_o;
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modport dut(input exclk_i, input capch_i, output irq_o);
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modport tb(input exclk_i, output capch_i, input irq_o);
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endinterface
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`endif
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@@ -0,0 +1,19 @@
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// Copyright (c) 2023-2024 Miao Yuchi <miaoyuchi@ict.ac.cn>
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// tmr is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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interface tmr_if (
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input logic exclk_i
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);
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logic capch_i;
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logic irq_o;
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modport dut(input exclk_i, input capch_i, output irq_o);
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modport tb(input exclk_i, output capch_i, input irq_o);
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endinterface
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