feat: add fifo, tx and rx module inst

rtl/apb4_uart.sv

@@ -73,10 +73,12 @@ module apb4_uart #(
   logic [31:0] s_uart_div_d, s_uart_div_q;
   logic [31:0] s_uart_fcr_d, s_uart_fcr_q;
   logic [31:0] s_uart_lsr_d, s_uart_lsr_q;
-  logic s_fifo_tx_valid, s_fifo_rx_valid, s_fifo_rx_ready, s_tx_ready, s_clr_int;
+  logic s_clr_int, s_parity_err;
+  logic s_tx_push_valid, s_tx_push_ready, s_tx_pop_valid, s_tx_pop_ready;
+  logic s_rx_pop_valid, s_rx_pop_ready;
   logic [2:0] s_lsr_ip;
-  logic [7:0] s_fifo_tx_data;
-  logic [8:0] s_fifo_rx_data;
+  logic [7:0] s_tx_push_data, s_tx_pop_data;
+  logic [8:0] s_rx_pop_data;
   logic [LOG_FIFO_DEPTH:0] s_tx_elem, s_rx_elem;
 
   assign s_apb4_addr = apb4.paddr[5:2];
@@ -85,7 +87,6 @@ module apb4_uart #(
   assign apb4.pready = 1'b1;
   assign apb4.pslverr = 1'b0;
 
-
   assign s_uart_lcr_d = (s_apb4_wr_hdshk && s_apb4_addr == `UART_LCR) ? apb4.pwdata : s_uart_lcr_q;
   dffr #(32) u_uart_lcr_dffr (
       apb4.pclk,
@@ -111,21 +112,20 @@ module apb4_uart #(
   );
 
   always_comb begin
-    s_fifo_tx_valid = 1'b0;
+    s_tx_push_valid = 1'b0;
     if (s_apb4_wr_hdshk && s_apb4_addr == `UART_TRX) begin
-      s_fifo_tx_valid = 1'b1;
-      s_fifo_tx_data  = apb4.pwdata[7:0];
+      s_tx_push_valid = 1'b1;
+      s_tx_push_data  = apb4.pwdata[7:0];
     end
   end
 
-
   always_comb begin
     s_uart_lsr_d      = s_uart_lsr_q;
     s_uart_lsr_d[2:0] = s_lsr_ip;
-    s_uart_lsr_d[3]   = s_fifo_rx_valid;
-    s_uart_lsr_d[4]   = s_fifo_rx_data[8];
+    s_uart_lsr_d[3]   = s_rx_pop_valid;
+    s_uart_lsr_d[4]   = s_rx_pop_data[8];
     s_uart_lsr_d[5]   = ~(|s_tx_elem);
-    s_uart_lsr_d[6]   = s_tx_ready & ~(|s_tx_elem);
+    s_uart_lsr_d[6]   = s_tx_pop_ready & ~(|s_tx_elem);
   end
   dffr #(32) u_uart_lsr_dffr (
       apb4.pclk,
@@ -134,18 +134,17 @@ module apb4_uart #(
       s_uart_lsr_q
   );
 
-
   always_comb begin
-    apb4.prdata     = '0;
-    s_fifo_rx_ready = 1'b0;
-    s_clr_int       = 1'b0;
+    apb4.prdata    = '0;
+    s_rx_pop_ready = 1'b0;
+    s_clr_int      = 1'b0;
     if (s_apb4_rd_hdshk) begin
       unique case (s_apb4_addr)
         `UART_LCR: apb4.prdata = s_uart_lcr_q;
         `UART_DIV: apb4.prdata = s_uart_div_q;
         `UART_TRX: begin
-          s_fifo_rx_ready = 1'b1;
-          apb4.prdata     = {24'b0, s_fifo_rx_data[7:0]};
+          s_rx_pop_ready = 1'b1;
+          apb4.prdata    = {24'b0, s_rx_pop_data[7:0]};
         end
         `UART_LSR: begin
           s_clr_int   = 1'b1;
@@ -155,6 +154,84 @@ module apb4_uart #(
     end
   end
 
-  
+  fifo #(
+      .DATA_WIDTH  (8),
+      .BUFFER_DEPTH(FIFO_DEPTH)
+  ) u_tx_fifo (
+      .clk_i  (apb4.pclk),
+      .rst_n_i(apb4.presetn),
+      .flush_i(s_uart_fcr_q[1]),
+      .cnt_o  (s_tx_elem),
+      .push_i (s_tx_push_valid),
+      .full_o (),
+      .dat_i  (s_tx_push_data),
+      .pop_i  (s_tx_pop_ready),
+      .empty_o(s_tx_pop_valid),
+      .dat_o  (s_tx_pop_data)
+  );
+
+  uart_tx u_uart_tx (
+      .clk_i          (apb4.pclk),
+      .rst_n_i        (apb4.presetn),
+      .tx_o           (uart_tx_o),
+      .busy_o         (),
+      .cfg_en_i       (1'b1),
+      .cfg_div_i      (s_uart_div_q[15:0]),
+      .cfg_parity_en_i(s_uart_lcr_q[6]),
+      .cfg_bits_i     (s_uart_lcr_q[4:3]),
+      .cfg_stop_bits_i(s_uart_lcr_q[5]),
+      .tx_data_i      (s_tx_pop_data),
+      .tx_valid_i     (s_tx_pop_valid),
+      .tx_ready_o     (s_tx_pop_ready)
+  );
+
+  fifo #(
+      .DATA_WIDTH  (9),
+      .BUFFER_DEPTH(FIFO_DEPTH)
+  ) u_rx_fifo (
+      .clk_i  (apb4.pclk),
+      .rst_n_i(apb4.presetn),
+      .flush_i(s_uart_fcr_q[0]),
+      .cnt_o  (s_rx_elem),
+      .push_i (s_rx_push_valid),
+      .full_o (s_rx_push_ready),
+      .dat_i  ({s_parity_err, s_rx_push_data}),
+      .pop_i  (s_rx_pop_ready),
+      .empty_o(s_rx_pop_valid),
+      .dat_o  (s_rx_pop_data)
+  );
+
+  uart_rx u_uart_rx (
+      .clk_i          (apb4.pclk),
+      .rst_n_i        (apb4.presetn),
+      .rx_i           (uart_rx_i),
+      .busy_o         (),
+      .cfg_div_i      (s_uart_div_q[15:0]),
+      .cfg_parity_en_i(s_uart_lcr_q[6]),
+      .cfg_bits_i     (s_uart_lcr_q[4:3]),
+      .cfg_stop_bits_i(s_uart_lcr_q[5]),
+      .err_o          (s_parity_err),
+      .err_clr_i      (1'b1),
+      .rx_data_o      (s_rx_push_data),
+      .rx_valid_o     (s_rx_push_valid),
+      .rx_ready_i     (s_rx_push_ready)
+  );
+
+  uart_irq #(
+      .FIFO_DEPTH(FIFO_DEPTH)
+  ) u_uart_irq (
+      .clk_i      (apb4.pclk),
+      .rst_n_i    (apb4.presetn),
+      .clr_int_i  (s_clr_int),
+      .irq_en_i   (s_uart_lcr_q[2:0]),
+      .thre_i     (s_uart_lsr_q[5]),
+      .cti_i      (1'b0),
+      .pe_i       (s_uart_lsr_q[4]),
+      .rx_elem_i  (s_rx_elem),
+      .tx_elem_i  (s_tx_elem),
+      .trg_level_i(s_uart_fcr_q[3:2]),
+      .ip_o       (s_lsr_ip),
+      .irq_o      (irq_o)
+  );
 endmodule