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82 lines
2.8 KiB
Systemverilog
82 lines
2.8 KiB
Systemverilog
// Copyright 2017 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the “License”); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// -- Adaptable modifications are redistributed under compatible License --
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//
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// Copyright (c) 2023 Beijing Institute of Open Source Chip
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// uart is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module uart_irq #(
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parameter FIFO_DEPTH = 16,
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parameter LOG_FIFO_DEPTH = $clog2(FIFO_DEPTH)
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) (
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input logic clk_i,
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input logic rst_n_i,
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input logic clr_int_i,
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input logic [ 2:0] irq_en_i,
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input logic thre_i,
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input logic cti_i,
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input logic pe_i,
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input logic [LOG_FIFO_DEPTH:0] rx_elem_i,
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input logic [LOG_FIFO_DEPTH:0] tx_elem_i,
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input logic [ 1:0] trg_level_i,
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output logic [ 2:0] ip_o,
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output logic irq_o
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);
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logic [2:0] s_ip_d, s_ip_q;
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logic s_trg_level_done;
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always_comb begin
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s_trg_level_done = 1'b0;
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unique case (trg_level_i)
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2'b00: if (rx_elem_i == 4'd1) s_trg_level_done = 1'b1;
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2'b01: if (rx_elem_i == 4'd2) s_trg_level_done = 1'b1;
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2'b10: if (rx_elem_i == 4'd8) s_trg_level_done = 1'b1;
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2'b11: if (rx_elem_i == 4'd14) s_trg_level_done = 1'b1;
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endcase
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end
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always_comb begin
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s_ip_d = s_ip_q;
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if (clr_int_i) begin
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s_ip_d = 3'b000;
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end else if (irq_en_i[2] & pe_i) begin
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s_ip_d = 3'b100;
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end else if (irq_en_i[0] & (s_trg_level_done | thre_i)) begin
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s_ip_d = 3'b001;
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end else if (irq_en_i[0] & cti_i) begin
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s_ip_d = 3'b001;
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end else if (irq_en_i[1] & tx_elem_i == 0) begin
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s_ip_d = 3'b010;
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end
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end
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dffr #(3) u_ip_dffr (
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clk_i,
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rstn_i,
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s_ip_d,
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s_ip_q
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);
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assign ip_o = s_ip_q;
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assign irq_o = s_ip_q != 3'b000;
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endmodule
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