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56 lines
1.4 KiB
Systemverilog
56 lines
1.4 KiB
Systemverilog
// Copyright (c) 2023 Beijing Institute of Open Source Chip
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// uart is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module rs232 #(
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parameter int BAUD_RATE = 115200,
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parameter int LOOPBACK = 0
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) (
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input logic rs232_rx_i,
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output logic rs232_tx_o
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);
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// unit: ns
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localparam DELAY_TIME = (10_0000_0000 / BAUD_RATE);
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logic [7:0] data;
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initial begin
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rs232_tx_o = 1'b1;
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end
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always @(negedge rs232_rx_i) begin
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receive(data);
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$write("%c", data);
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if (LOOPBACK) send(data);
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end
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task automatic receive(output bit [7:0] value);
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begin
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value = '0;
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#(DELAY_TIME * 1.5);
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for (int i = 0; i < 8; i++) begin
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value[i] = rs232_rx_i;
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#(DELAY_TIME);
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end
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end
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endtask
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task automatic send(input bit [7:0] value);
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begin
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rs232_tx_o = 1'b0;
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#(DELAY_TIME);
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for (int i = 0; i < 8; i++) begin
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rs232_tx_o = value[i];
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#(DELAY_TIME);
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end
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rs232_tx_o = 1'b1;
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#(DELAY_TIME);
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end
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endtask
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endmodule
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