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238 lines
7.7 KiB
Systemverilog
238 lines
7.7 KiB
Systemverilog
// Copyright 2017 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the “License”); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// -- Adaptable modifications are redistributed under compatible License --
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//
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// Copyright (c) 2023 Beijing Institute of Open Source Chip
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// uart is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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// verilog_format: off
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`define UART_LCR 4'b0000 //BASEADDR+0x00
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`define UART_DIV 4'b0001 //BASEADDR+0x08
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`define UART_TRX 4'b0010 //BASEADDR+0x04
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`define UART_FCR 4'b0011 //BASEADDR+0x0C
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`define UART_LSR 4'b0100 //BASEADDR+0x10
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// verilog_format: on
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/* register mapping
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* UART_LCR:
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* BITS: | 31:9 | 8:7 | 6 | 5 | 4:3 | 2 | 1 | 0 |
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* FIELDS: | RES | PS | PEN | STB | WLS | PEIE | TXIE | RXIE |
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* PERMS: | NONE | RW | RW | RW | RW | RW | RW | RW |
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* ----------------------------------------------------------------
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* UART_DIV:
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* BITS: | 31:16 | 15:0 |
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* FIELDS: | RES | DIV |
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* PERMS: | NONE | RW |
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* ----------------------------------------------------------------
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* UART_FCR:
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* BITS: | 31:4 | 3:2 | 1 | 0 |
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* FIELDS: | RES | RX_TRG_LEVL | TF_CLR | RF_CLR |
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* PERMS: | NONE | W | W | W |
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* ----------------------------------------------------------------
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* UART_TRX:
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* BITS: | 31:8 | 7:0 || BITS: | 31:8 | 7:0 |
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* FIELDS: | RES | RX || FIELDS: | RES | TX |
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* PERMS: | NONE | R || PERMS: | NONE | W |
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* ----------------------------------------------------------------
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* UART_LSR:
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* BITS: | 31:7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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* FIELDS: | RES | TEMT | THRE | PE | DR | PEIP | TXIP | RXIP |
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* PERMS: | NONE | R | R | R | R | R | R | R |
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* ----------------------------------------------------------------
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*/
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module apb4_uart #(
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parameter int FIFO_DEPTH = 16,
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parameter int LOG_FIFO_DEPTH = $clog2(FIFO_DEPTH)
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) (
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// verilog_format: off
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apb4_if.slave apb4,
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// verilog_format: on
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input logic uart_rx_i,
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output logic uart_tx_o,
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output logic irq_o
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);
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logic [3:0] s_apb4_addr;
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logic [31:0] s_uart_lcr_d, s_uart_lcr_q;
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logic [31:0] s_uart_trx_d, s_uart_trx_q;
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logic [31:0] s_uart_div_d, s_uart_div_q;
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logic [31:0] s_uart_fcr_d, s_uart_fcr_q;
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logic [31:0] s_uart_lsr_d, s_uart_lsr_q;
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logic s_clr_int, s_parity_err;
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logic s_tx_push_valid, s_tx_push_ready, s_tx_pop_valid, s_tx_pop_ready;
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logic s_rx_pop_valid, s_rx_pop_ready;
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logic [2:0] s_lsr_ip;
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logic [7:0] s_tx_push_data, s_tx_pop_data;
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logic [8:0] s_rx_pop_data;
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logic [LOG_FIFO_DEPTH:0] s_tx_elem, s_rx_elem;
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assign s_apb4_addr = apb4.paddr[5:2];
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assign s_apb4_wr_hdshk = apb4.psel && apb4.penable && apb4.pwrite;
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assign s_apb4_rd_hdshk = apb4.psel && apb4.penable && (~apb4.pwrite);
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assign apb4.pready = 1'b1;
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assign apb4.pslverr = 1'b0;
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assign s_uart_lcr_d = (s_apb4_wr_hdshk && s_apb4_addr == `UART_LCR) ? apb4.pwdata : s_uart_lcr_q;
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dffr #(32) u_uart_lcr_dffr (
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apb4.pclk,
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apb4.presetn,
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s_uart_lcr_d,
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s_uart_lcr_q
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);
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assign s_uart_div_d = (s_apb4_wr_hdshk && s_apb4_addr == `UART_DIV) ? apb4.pwdata : s_uart_div_q;
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dffr #(32) u_uart_div_dffr (
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apb4.pclk,
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apb4.presetn,
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s_uart_div_d,
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s_uart_div_q
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);
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assign s_uart_fcr_d = (s_apb4_wr_hdshk && s_apb4_addr == `UART_FCR) ? apb4.pwdata : s_uart_fcr_q;
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dffr #(32) u_uart_fcr_dffr (
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apb4.pclk,
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apb4.presetn,
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s_uart_fcr_d,
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s_uart_fcr_q
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);
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always_comb begin
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s_tx_push_valid = 1'b0;
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if (s_apb4_wr_hdshk && s_apb4_addr == `UART_TRX) begin
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s_tx_push_valid = 1'b1;
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s_tx_push_data = apb4.pwdata[7:0];
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end
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end
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always_comb begin
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s_uart_lsr_d = s_uart_lsr_q;
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s_uart_lsr_d[2:0] = s_lsr_ip;
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s_uart_lsr_d[3] = s_rx_pop_valid;
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s_uart_lsr_d[4] = s_rx_pop_data[8];
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s_uart_lsr_d[5] = ~(|s_tx_elem);
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s_uart_lsr_d[6] = s_tx_pop_ready & ~(|s_tx_elem);
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end
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dffr #(32) u_uart_lsr_dffr (
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apb4.pclk,
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apb4.presetn,
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s_uart_lsr_d,
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s_uart_lsr_q
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);
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always_comb begin
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apb4.prdata = '0;
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s_rx_pop_ready = 1'b0;
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s_clr_int = 1'b0;
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if (s_apb4_rd_hdshk) begin
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unique case (s_apb4_addr)
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`UART_LCR: apb4.prdata = s_uart_lcr_q;
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`UART_DIV: apb4.prdata = s_uart_div_q;
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`UART_TRX: begin
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s_rx_pop_ready = 1'b1;
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apb4.prdata = {24'b0, s_rx_pop_data[7:0]};
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end
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`UART_LSR: begin
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s_clr_int = 1'b1;
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apb4.prdata = s_uart_lsr_q;
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end
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endcase
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end
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end
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fifo #(
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.DATA_WIDTH (8),
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.BUFFER_DEPTH(FIFO_DEPTH)
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) u_tx_fifo (
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.clk_i (apb4.pclk),
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.rst_n_i(apb4.presetn),
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.flush_i(s_uart_fcr_q[1]),
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.cnt_o (s_tx_elem),
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.push_i (s_tx_push_valid),
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.full_o (),
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.dat_i (s_tx_push_data),
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.pop_i (s_tx_pop_ready),
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.empty_o(s_tx_pop_valid),
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.dat_o (s_tx_pop_data)
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);
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uart_tx u_uart_tx (
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.clk_i (apb4.pclk),
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.rst_n_i (apb4.presetn),
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.tx_o (uart_tx_o),
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.busy_o (),
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.cfg_en_i (1'b1),
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.cfg_div_i (s_uart_div_q[15:0]),
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.cfg_parity_en_i(s_uart_lcr_q[6]),
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.cfg_bits_i (s_uart_lcr_q[4:3]),
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.cfg_stop_bits_i(s_uart_lcr_q[5]),
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.tx_data_i (s_tx_pop_data),
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.tx_valid_i (s_tx_pop_valid),
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.tx_ready_o (s_tx_pop_ready)
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);
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fifo #(
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.DATA_WIDTH (9),
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.BUFFER_DEPTH(FIFO_DEPTH)
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) u_rx_fifo (
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.clk_i (apb4.pclk),
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.rst_n_i(apb4.presetn),
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.flush_i(s_uart_fcr_q[0]),
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.cnt_o (s_rx_elem),
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.push_i (s_rx_push_valid),
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.full_o (s_rx_push_ready),
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.dat_i ({s_parity_err, s_rx_push_data}),
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.pop_i (s_rx_pop_ready),
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.empty_o(s_rx_pop_valid),
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.dat_o (s_rx_pop_data)
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);
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uart_rx u_uart_rx (
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.clk_i (apb4.pclk),
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.rst_n_i (apb4.presetn),
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.rx_i (uart_rx_i),
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.busy_o (),
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.cfg_div_i (s_uart_div_q[15:0]),
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.cfg_parity_en_i(s_uart_lcr_q[6]),
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.cfg_bits_i (s_uart_lcr_q[4:3]),
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.cfg_stop_bits_i(s_uart_lcr_q[5]),
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.err_o (s_parity_err),
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.err_clr_i (1'b1),
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.rx_data_o (s_rx_push_data),
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.rx_valid_o (s_rx_push_valid),
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.rx_ready_i (s_rx_push_ready)
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);
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uart_irq #(
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.FIFO_DEPTH(FIFO_DEPTH)
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) u_uart_irq (
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.clk_i (apb4.pclk),
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.rst_n_i (apb4.presetn),
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.clr_int_i (s_clr_int),
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.irq_en_i (s_uart_lcr_q[2:0]),
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.thre_i (s_uart_lsr_q[5]),
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.cti_i (1'b0),
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.pe_i (s_uart_lsr_q[4]),
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.rx_elem_i (s_rx_elem),
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.tx_elem_i (s_tx_elem),
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.trg_level_i(s_uart_fcr_q[3:2]),
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.ip_o (s_lsr_ip),
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.irq_o (irq_o)
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);
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endmodule
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