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49 lines
1.1 KiB
Systemverilog
49 lines
1.1 KiB
Systemverilog
// Copyright (c) 2023 Beijing Institute of Open Source Chip
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// uart is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "apb4_if.sv"
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`include "uart_define.sv"
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module apb4_uart_tb ();
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localparam CLK_PEROID = 10;
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logic rst_n_i, clk_i;
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initial begin
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clk_i = 1'b0;
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forever begin
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#(CLK_PEROID / 2) clk_i <= ~clk_i;
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end
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end
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task sim_reset(int delay);
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rst_n_i = 1'b0;
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repeat (delay) @(posedge clk_i);
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#1 rst_n_i = 1'b1;
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endtask
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initial begin
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sim_reset(40);
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end
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apb4_if u_apb4_if (
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clk_i,
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rst_n_i
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);
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uart_if u_uart_if ();
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test_top u_test_top (.apb4(u_apb4_if.master));
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apb4_uart u_apb4_uart (
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.apb4(u_apb4_if.slave),
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.uart(u_uart_if.dut)
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);
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endmodule
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