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88 lines
2.0 KiB
Systemverilog
88 lines
2.0 KiB
Systemverilog
// Copyright (c) 2023 Beijing Institute of Open Source Chip
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// uart is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module rs232_tb ();
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localparam BAUD_RATE = 115200;
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localparam DELAY_TIME = (10_0000_0000 / BAUD_RATE);
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string wave_name = "default.fsdb";
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logic rs232_tx, rs232_rx;
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logic [7:0] data;
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bit [7:0] wr_val;
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task sim_config();
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$timeformat(-9, 1, "ns", 10);
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if ($test$plusargs("WAVE_ON")) begin
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$value$plusargs("WAVE_NAME=%s", wave_name);
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$fsdbDumpfile(wave_name);
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$fsdbDumpvars("+all");
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end
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endtask
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task automatic send(input bit [7:0] value);
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begin
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rs232_tx = 1'b0;
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#(DELAY_TIME);
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for (int i = 0; i < 8; i++) begin
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rs232_tx = value[i];
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#(DELAY_TIME);
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end
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rs232_tx = 1'b1;
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#(DELAY_TIME);
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end
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endtask
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task automatic receive(output bit [7:0] value);
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begin
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value = '0;
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#(DELAY_TIME * 1.5);
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for (int i = 0; i < 8; i++) begin
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value[i] = rs232_rx;
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#(DELAY_TIME);
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end
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end
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endtask
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always @(negedge rs232_rx) begin
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receive(data);
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$write("[REC]: %c", data);
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end
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task automatic test_rx();
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wr_val = 8'h41;
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for (int i = 0; i < 6; i++) begin
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for (int j = 0; j < 25; j++) begin
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send(wr_val + j);
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#200;
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end
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send(8'h0A);
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end
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endtask
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task automatic test_tx();
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u_rs232.send(8'h42);
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endtask
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initial begin
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sim_config();
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test_rx();
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test_tx();
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#2000000 $finish;
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end
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rs232 #(115200, 0) u_rs232 (
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.rs232_rx_i(rs232_tx),
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.rs232_tx_o(rs232_rx)
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);
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endmodule
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