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https://github.com/retroSoC/uart.git
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74 lines
2.7 KiB
Systemverilog
74 lines
2.7 KiB
Systemverilog
// Copyright (c) 2023 Beijing Institute of Open Source Chip
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// uart is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`ifndef INC_UART_DEF_SV
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`define INC_UART_DEF_SV
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/* register mapping
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* UART_LCR:
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* BITS: | 31:9 | 8:7 | 6 | 5 | 4:3 | 2 | 1 | 0 |
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* FIELDS: | RES | PS | PEN | STB | WLS | PEIE | TXIE | RXIE |
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* PERMS: | NONE | RW | RW | RW | RW | RW | RW | RW |
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* --------------------------------------------------------------
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* UART_DIV:
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* BITS: | 31:16 | 15:0 |
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* FIELDS: | RES | DIV |
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* PERMS: | NONE | RW |
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* --------------------------------------------------------------
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* UART_TRX:
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* BITS: | 31:8 | 7:0 || BITS: | 31:8 | 7:0 |
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* FIELDS: | RES | RX || FIELDS: | RES | TX |
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* PERMS: | NONE | R || PERMS: | NONE | W |
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* -------------------------------------------------------------
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* UART_FCR:
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* BITS: | 31:4 | 3:2 | 1 | 0 |
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* FIELDS: | RES | RX_TRG_LEVL | TF_CLR | RF_CLR |
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* PERMS: | NONE | W | W | W |
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* --------------------------------------------------------------
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* UART_LSR:
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* BITS: | 31:7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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* FIELDS: | RES | TEMT | THRE | PE | DR | PEIP | TXIP | RXIP |
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* PERMS: | NONE | R | R | R | R | R | R | R |
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* --------------------------------------------------------------
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*/
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// verilog_format: off
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`define UART_LCR 4'b0000 // BASEADDR + 0x00
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`define UART_DIV 4'b0001 // BASEADDR + 0x08
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`define UART_TRX 4'b0010 // BASEADDR + 0x04
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`define UART_FCR 4'b0011 // BASEADDR + 0x0C
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`define UART_LSR 4'b0100 // BASEADDR + 0x10
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`define UART_LCR_ADDR {26'b0, `UART_LCR, 2'b00}
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`define UART_DIV_ADDR {26'b0, `UART_DIV, 2'b00}
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`define UART_TRX_ADDR {26'b0, `UART_TRX, 2'b00}
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`define UART_FCR_ADDR {26'b0, `UART_FCR, 2'b00}
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`define UART_LSR_ADDR {26'b0, `UART_LSR, 2'b00}
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`define UART_LCR_WIDTH 9
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`define UART_DIV_WIDTH 16
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`define UART_TRX_WIDTH 8
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`define UART_FCR_WIDTH 4
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`define UART_LSR_WIDTH 7
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`define UART_DIV_MIN_VAL {{(`UART_DIV_WIDTH-2){1'b0}}, 2'd2}
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`define UART_LSR_RESET_VAL 7'h60
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// verilog_format: on
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interface uart_if ();
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logic uart_rx_i;
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logic uart_tx_o;
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logic irq_o;
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modport dut(input uart_rx_i, output uart_tx_o, output irq_o);
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modport tb(output uart_rx_i, input uart_tx_o, input irq_o);
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endinterface
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`endif
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