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https://github.com/retroSoC/uart.git
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55 lines
1.8 KiB
Systemverilog
55 lines
1.8 KiB
Systemverilog
// Copyright (c) 2023 Beijing Institute of Open Source Chip
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// uart is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`ifndef INC_UART_TEST_SV
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`define INC_UART_TEST_SV
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`include "apb4_master.sv"
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`include "uart_define.sv"
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class UARTTest extends APB4Master;
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string name;
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int wr_val;
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virtual apb4_if.master apb4;
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extern function new(string name = "pwm_test", virtual apb4_if.master apb4);
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extern task automatic test_reset_reg();
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extern task automatic test_wr_rd_reg(input bit [31:0] run_times = 1000);
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extern task automatic test_irq(input bit [31:0] run_times = 10);
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endclass
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function UARTTest::new(string name, virtual apb4_if.master apb4);
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super.new("apb4_master", apb4);
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this.name = name;
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this.wr_val = 0;
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this.apb4 = apb4;
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endfunction
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task automatic UARTTest::test_reset_reg();
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super.test_reset_reg();
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// verilog_format: off
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// this.rd_check(`PWM_CTRL_ADDR, "CTRL REG", 32'b0 & {`PWM_CTRL_WIDTH{1'b1}}, Helper::EQUL, Helper::INFO);
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// verilog_format: on
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endtask
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task automatic UARTTest::test_wr_rd_reg(input bit [31:0] run_times = 1000);
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super.test_wr_rd_reg();
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// verilog_format: off
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for (int i = 0; i < run_times; i++) begin
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// this.wr_rd_check(`PWM_CTRL_ADDR, "CTRL REG", $random & {`PWM_CTRL_WIDTH{1'b1}}, Helper::EQUL);
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end
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// verilog_format: on
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endtask
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task automatic UARTTest::test_irq(input bit [31:0] run_times = 10);
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super.test_irq();
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endtask
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`endif
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