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feat: replace reg delay value to the marcro define

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maksyuki committed 2024-08-16 12:19:31 +08:00
1 parent a8af6b3359
commit ac5ccade08
5 files changed
+34 -27
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rtl/cdc/cdc_2phase.sv
+7 -6
View File
@@ -26,6 +26,7 @@
`ifndef INC_CDC_TWOPHASE_SV
`define INC_CDC_TWOPHASE_SV
`include "setting.sv"
`include "register.sv"
`include "cdc_sync.sv"
@@ -161,13 +162,13 @@ module cdc_2phase_dst #(
// The req_dst and req registers act as synchronization stages.
always_ff @(posedge clk_i or negedge rst_n_i) begin
if (!rst_n_i) begin
r_req_dst_q <= '0;
r_req_q0 <= '0;
r_req_q1 <= '0;
r_req_dst_q <= #`REGISTER_DELAY '0;
r_req_q0 <= #`REGISTER_DELAY '0;
r_req_q1 <= #`REGISTER_DELAY '0;
end else begin
r_req_dst_q <= async_req_i;
r_req_q0 <= r_req_dst_q;
r_req_q1 <= r_req_q0;
r_req_dst_q <= #`REGISTER_DELAY async_req_i;
r_req_q0 <= #`REGISTER_DELAY r_req_dst_q;
r_req_q1 <= #`REGISTER_DELAY r_req_q0;
end
end
rtl/interface/axi4_slv_fsm.sv
+5 -4
View File
@@ -23,6 +23,7 @@
`ifndef INC_AXI4_SLV_FSM_SV
`define INC_AXI4_SLV_FSM_SV
`include "setting.sv"
`include "register.sv"
`include "axi4_define.sv"
`include "axi4_addr_gen.sv"
@@ -266,11 +267,11 @@ module axi4_slv_fsm #(
always_ff @(posedge aclk, negedge aresetn) begin
if (~aresetn) begin
s_state_q <= #1 IDLE;
s_axi_req_q <= #1'0;
s_state_q <= #`REGISTER_DELAY IDLE;
s_axi_req_q <= #`REGISTER_DELAY '0;
end else begin
s_state_q <= #1 s_state_d;
s_axi_req_q <= #1 s_axi_req_d;
s_state_q <= #`REGISTER_DELAY s_state_d;
s_axi_req_q <= #`REGISTER_DELAY s_axi_req_d;
end
end
endmodule
rtl/tech/ram.sv
+6 -4
View File
@@ -11,6 +11,8 @@
`ifndef INC_TECH_RAM_SV
`define INC_TECH_RAM_SV
`include "setting.sv"
// this file only include behavioral model, for ASIC tape-out need to reimplement those models
module tech_ram #(
parameter int BIT_WIDTH = 128,
@@ -31,9 +33,9 @@ module tech_ram #(
logic [BIT_WIDTH-1:0] r_intern_ram[0:WORD_DEPTH-1];
always_ff @(posedge clk_i) begin
if (~en_i && ~wen_i) begin
r_intern_ram[addr_i] <= dat_i;
r_intern_ram[addr_i] <= #`REGISTER_DELAY dat_i;
end else begin
dat_o <= (~en_i && wen_i) ? r_intern_ram[addr_i] : {(BIT_WIDTH / 32) {$random}};
dat_o <= #`REGISTER_DELAY (~en_i && wen_i) ? r_intern_ram[addr_i] : {(BIT_WIDTH / 32) {$random}};
end
end
`endif
@@ -64,9 +66,9 @@ module tech_ram_bm #(
always_ff @(posedge clk_i) begin
if (~en_i && ~wen_i) begin
r_intern_ram[addr_i] <= s_dat_i;
r_intern_ram[addr_i] <= #`REGISTER_DELAY s_dat_i;
end else begin
dat_o <= (~en_i && wen_i) ? r_intern_ram[addr_i] : {(BIT_WIDTH / 32) {$random}};
dat_o <= #`REGISTER_DELAY (~en_i && wen_i) ? r_intern_ram[addr_i] : {(BIT_WIDTH / 32) {$random}};
end
end
`endif
rtl/tech/regfile.sv
+6 -4
View File
@@ -11,6 +11,8 @@
`ifndef INC_REGFILE_SV
`define INC_REGFILE_SV
`include "setting.sv"
// this file only include behavioral model, for ASIC tape-out need to reimplement those models
module tech_regfile #(
parameter int BIT_WIDTH = 128,
@@ -31,9 +33,9 @@ module tech_regfile #(
logic [BIT_WIDTH-1:0] r_intern_ram[0:WORD_DEPTH-1];
always_ff @(posedge clk_i) begin
if (~en_i && ~wen_i) begin
r_intern_ram[addr_i] <= #1 dat_i;
r_intern_ram[addr_i] <= #`REGISTER_DELAY dat_i;
end else begin
dat_o <= #1 (~en_i && wen_i) ? r_intern_ram[addr_i] : {(BIT_WIDTH / 32) {$random}};
dat_o <= #`REGISTER_DELAY (~en_i && wen_i) ? r_intern_ram[addr_i] : {(BIT_WIDTH / 32) {$random}};
end
end
`endif
@@ -70,9 +72,9 @@ module tech_regfile_bm #(
always_ff @(posedge clk_i) begin
if (s_en && s_wen) begin
r_intern_ram[addr_i] <= #1 (dat_i & s_bm) | (r_intern_ram[addr_i] & ~s_bm);
r_intern_ram[addr_i] <= #`REGISTER_DELAY (dat_i & s_bm) | (r_intern_ram[addr_i] & ~s_bm);
end
dat_o <= #1 (s_en && ~s_wen) ? r_intern_ram[addr_i] : {(BIT_WIDTH / 32) {$random}};
dat_o <= #`REGISTER_DELAY (s_en && ~s_wen) ? r_intern_ram[addr_i] : {(BIT_WIDTH / 32) {$random}};
end
`endif
endmodule
rtl/verif/axi4_master.sv
+10 -9
View File
@@ -11,6 +11,7 @@
`ifndef INC_AXI4_MASTER_SV
`define INC_AXI4_MASTER_SV
`include "setting.sv"
`include "helper.sv"
`include "test_base.sv"
`include "axi4_define.sv"
@@ -147,7 +148,7 @@ task automatic AXI4Master::write(
// aw channel
@(posedge this.axi4.aclk);
#1;
#`REGISTER_DELAY;
this.axi4.awid = id;
this.axi4.awaddr = addr;
this.axi4.awlen = len - 1;
@@ -159,7 +160,7 @@ task automatic AXI4Master::write(
while (~this.axi4.awready) begin
@(posedge this.axi4.aclk);
end
#1;
#`REGISTER_DELAY;
// $display("%t aw trigger", $time);
this.axi4.awid = '0;
this.axi4.awaddr = 'x;
@@ -168,7 +169,7 @@ task automatic AXI4Master::write(
this.axi4.awburst = `AXI4_BURST_TYPE_FIXED;
this.axi4.awvalid = '0;
@(negedge this.axi4.aclk);
#1;
#`REGISTER_DELAY;
// w burst channel
tmp_addr = addr;
for (int i = 0; i < len; i++) begin
@@ -181,7 +182,7 @@ task automatic AXI4Master::write(
while (~this.axi4.wready) begin
@(posedge this.axi4.aclk);
end
#1;
#`REGISTER_DELAY;
// $display("%t w burst trigger", $time);
end
@@ -209,7 +210,7 @@ task automatic AXI4Master::write(
`AXI4_RESP_DECODE_ERROR: $display("%t DECERR", $time);
endcase
end
#1;
#`REGISTER_DELAY;
this.axi4.bready = 1'b0;
@(negedge this.axi4.aclk);
endtask
@@ -223,7 +224,7 @@ task automatic AXI4Master::read(input bit [`AXI4_ID_WIDTH-1:0] id,
this.rd_data = {};
// ar channel
@(posedge this.axi4.aclk);
#1;
#`REGISTER_DELAY;
this.axi4.arid = id;
this.axi4.araddr = addr;
this.axi4.arlen = len - 1;
@@ -235,7 +236,7 @@ task automatic AXI4Master::read(input bit [`AXI4_ID_WIDTH-1:0] id,
while (~this.axi4.arready) begin
@(posedge this.axi4.aclk);
end
#1;
#`REGISTER_DELAY;
// $display("%t ar trigger", $time);
this.axi4.arid = '0;
this.axi4.araddr = 'x;
@@ -248,7 +249,7 @@ task automatic AXI4Master::read(input bit [`AXI4_ID_WIDTH-1:0] id,
// r burst channel
tmp_addr = addr;
@(posedge this.axi4.aclk);
#1;
#`REGISTER_DELAY;
this.axi4.rready = 1'b1;
for (int i = 0; i < len; i++) begin
@(posedge this.axi4.aclk);
@@ -271,7 +272,7 @@ task automatic AXI4Master::read(input bit [`AXI4_ID_WIDTH-1:0] id,
@(negedge this.axi4.aclk);
tmp_addr = this.calc_addr(tmp_addr, size, burst);
end
#1;
#`REGISTER_DELAY;
end
this.axi4.rready = 1'b0;