feat: replace reg delay value to the marcro define

rtl/cdc/cdc_2phase.sv

@@ -26,6 +26,7 @@
 `ifndef INC_CDC_TWOPHASE_SV
 `define INC_CDC_TWOPHASE_SV
 
+`include "setting.sv"
 `include "register.sv"
 `include "cdc_sync.sv"
 
@@ -161,13 +162,13 @@ module cdc_2phase_dst #(
   // The req_dst and req registers act as synchronization stages.
   always_ff @(posedge clk_i or negedge rst_n_i) begin
     if (!rst_n_i) begin
-      r_req_dst_q <= '0;
-      r_req_q0    <= '0;
-      r_req_q1    <= '0;
+      r_req_dst_q <= #`REGISTER_DELAY '0;
+      r_req_q0    <= #`REGISTER_DELAY '0;
+      r_req_q1    <= #`REGISTER_DELAY '0;
     end else begin
-      r_req_dst_q <= async_req_i;
-      r_req_q0    <= r_req_dst_q;
-      r_req_q1    <= r_req_q0;
+      r_req_dst_q <= #`REGISTER_DELAY async_req_i;
+      r_req_q0    <= #`REGISTER_DELAY r_req_dst_q;
+      r_req_q1    <= #`REGISTER_DELAY r_req_q0;
     end
   end