- Added geometry validation for BIT_WIDTH, WORD_DEPTH, and ADDR_WIDTH in tech_ram, tech_ram_bm, tech_regfile, and tech_regfile_bm modules to ensure proper configurations.
- Implemented address range checks in tech_ram, tech_ram_bm, tech_regfile, and tech_regfile_bm modules to prevent out-of-bounds access.
- Improved error messages for unsupported access types in regfield module, including validation for DATA_WIDTH.
- Added DATA_WIDTH validation in spill_register module to ensure positive values.
- Refactored APB4AXI4Master and APB4Master classes to streamline constructor definitions and improve readability.
- Enhanced AXI4Master class with additional burst address calculations and legality checks for read/write operations.
- Updated read/write tasks in AXI4Master to include error handling for response mismatches and illegal burst conditions.
- Simplified the filtering of reference data in rd_check task of AXI4Master to improve clarity and maintainability.
- Cleaned up the TestBase class constructor for consistency and clarity.
- Updated license headers to use SPDX format across all RTL files.
- Enhanced error checking in various modules (e.g., tech_ram, tech_regfile, bin2gray, gray2bin, lfsr) to validate parameters and prevent invalid configurations.
- Refactored FIFO implementation to simplify pointer management and ensure proper handling of push/pop operations.
- Introduced new scripts for checking formatting and license headers, ensuring compliance with project standards.
- Added style guidelines to maintain consistent coding practices across the RTL codebase.
- Updated testbench files to include license headers and maintain compatibility with legacy structures.
maksyuki