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maksyuki
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- Created documentation for , , , and modules, detailing their functionality, parameters, and usage examples. - Implemented a script to ensure required headings and content are present in documentation files. - Developed to generate and update documentation pages from SystemVerilog declarations, ensuring consistency and completeness.
85 lines
2.8 KiB
Markdown
85 lines
2.8 KiB
Markdown
# address_map
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| Property | Value |
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| --- | --- |
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| Kind | `module` |
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| RTL source | [`rtl/bus/address_decode.sv`](../../../rtl/bus/address_decode.sv) |
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| Availability | Synthesizable RTL |
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## Summary
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Masked address-map decoder with deterministic lowest-index priority.
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## Functional Behavior
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Masked address-map decoder with deterministic lowest-index priority. It classifies the presented address using the configured decode rule and returns the documented selection/match result combinationally.
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## Suitable Applications
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Use for memory maps, peripheral selection, firewall regions, and target routing.
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## Parameters
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The declaration below is canonical; retain the RTL-enforced parameter range.
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| Parameter | Declaration |
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| --- | --- |
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| `ADDR_WIDTH` | `parameter int ADDR_WIDTH = 32` |
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| `REGIONS` | `parameter int REGIONS = 4` |
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| `INDEX_WIDTH` | `parameter int INDEX_WIDTH = (REGIONS > 1) ? $clog2(REGIONS) : 1` |
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## Interface Definition
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```systemverilog
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module address_map #(
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parameter int ADDR_WIDTH = 32,
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parameter int REGIONS = 4,
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parameter int INDEX_WIDTH = (REGIONS > 1) ? $clog2(REGIONS) : 1
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) (
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input logic [ ADDR_WIDTH-1:0] addr_i,
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input logic [ REGIONS-1:0][ADDR_WIDTH-1:0] base_i,
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input logic [ REGIONS-1:0][ADDR_WIDTH-1:0] mask_i,
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output logic [ REGIONS-1:0] hit_o,
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output logic [INDEX_WIDTH-1:0] selected_o,
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output logic valid_o
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);
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```
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### Port Summary
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| Signal | Direction | Declaration |
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| --- | --- | --- |
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| `addr_i` | `input` | `input logic [ ADDR_WIDTH-1:0] addr_i` |
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| `base_i` | `input` | `input logic [ REGIONS-1:0][ADDR_WIDTH-1:0] base_i` |
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| `mask_i` | `input` | `input logic [ REGIONS-1:0][ADDR_WIDTH-1:0] mask_i` |
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| `hit_o` | `output` | `output logic [ REGIONS-1:0] hit_o` |
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| `selected_o` | `output` | `output logic [INDEX_WIDTH-1:0] selected_o` |
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| `valid_o` | `output` | `output logic valid_o` |
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## Integration and Use
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Check overlaps and priority deliberately. Decode does not by itself complete or validate a bus transaction.
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```systemverilog
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address_map #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.REGIONS(REGIONS),
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.INDEX_WIDTH(INDEX_WIDTH)
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) u_address_map (
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.addr_i(addr_i),
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.base_i(base_i),
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.mask_i(mask_i),
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.hit_o(hit_o),
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.selected_o(selected_o),
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.valid_o(valid_o)
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);
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```
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## Dependencies and Verification
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The linked RTL source is the implementation authority and contains local assertions for unsupported
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parameter combinations. See [`docs/design.md`](../../design.md) for repository-wide CDC, reset,
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stream, and storage contracts, and [`docs/verification.md`](../../verification.md) for the
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verification matrix.
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