Files
maksyuki 3b6a925a51 feat: add documentation for new utility components and scripts
- Created documentation for , , , and  modules, detailing their functionality, parameters, and usage examples.
- Implemented a script  to ensure required headings and content are present in documentation files.
- Developed  to generate and update documentation pages from SystemVerilog declarations, ensuring consistency and completeness.
2026-08-04 16:35:53 +08:00

1.6 KiB

xchecker

Property Value
Kind module
RTL source rtl/utils/xchecker.sv
Availability Simulation/verification model

Summary

Simulation unknown-value checker.

Functional Behavior

Simulation unknown-value checker. Its exact parameters and ports are reproduced below from the implementation declaration.

Suitable Applications

Use as a small reusable datapath, state, coding, delay, or verification primitive.

Parameters

The declaration below is canonical; retain the RTL-enforced parameter range.

Parameter Declaration
DATA_WIDTH parameter DATA_WIDTH = 1

Interface Definition

module xchecker #(
    parameter DATA_WIDTH = 1
) (
    input logic                  clk_i,
    input logic [DATA_WIDTH-1:0] dat_i
);

Port Summary

Signal Direction Declaration
clk_i input input logic clk_i
dat_i input input logic [DATA_WIDTH-1:0] dat_i

Integration and Use

Keep parameter values within RTL assertions and add required clocking, reset, or CDC protection at the caller boundary.

xchecker #(
    .DATA_WIDTH(DATA_WIDTH)
) u_xchecker (
    .clk_i(clk_i),
    .dat_i(dat_i)
);

Dependencies and Verification

The linked RTL source is the implementation authority and contains local assertions for unsupported parameter combinations. See docs/design.md for repository-wide CDC, reset, stream, and storage contracts, and docs/verification.md for the verification matrix.