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73 lines
1.4 KiB
Systemverilog
73 lines
1.4 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// common is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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interface ahbl_if (
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input logic hclk,
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input logic hresetn
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);
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logic [31:0] haddr;
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logic hwrite;
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logic [ 2:0] hsize;
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logic [ 2:0] hburst;
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logic [ 3:0] hprot;
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logic [ 1:0] htrans;
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logic hmastlock;
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logic [31:0] hwdata;
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logic hready;
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logic hresp;
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logic [31:0] hrdata;
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modport slave(
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input hclk,
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input hresetn,
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input haddr,
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input hwrite,
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input hsize,
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input hburst,
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input hprot,
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input htrans,
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input hmastlock,
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input hwdata,
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output hready,
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output hresp,
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output hrdata
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);
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modport master(
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input hclk,
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input hresetn,
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output haddr,
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output hwrite,
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output hsize,
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output hburst,
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output hprot,
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output htrans,
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output hmastlock,
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output hwdata,
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input hready,
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input hresp,
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input hrdata
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);
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endinterface
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