mirror of
https://github.com/retroSoC/common.git
synced 2026-11-04 22:32:37 +00:00
maksyuki
3b6a925a51
- Created documentation for , , , and modules, detailing their functionality, parameters, and usage examples. - Implemented a script to ensure required headings and content are present in documentation files. - Developed to generate and update documentation pages from SystemVerilog declarations, ensuring consistency and completeness.
RTL Reference
One checked-in page exists for every declared SystemVerilog module, interface, and package under rtl/. The pages mirror RTL categories and reproduce the canonical source declaration.
After changing a declaration or its integration contract, run python3 scripts/render_component_docs.py and then make docs-check. The latter rejects stale pages, missing coverage, malformed required sections, and a stale README catalog.
rtl/verif contains class-based verification support rather than RTL declarations. rtl/clkrst/clk_frac_div.sv is a compatibility source with no declaration because fractional division is intentionally not provided.
Categories
base:bit_count,component_math_pkg,counting_bloom_filter,credit_pool,hash_indicator_bank,index_to_onehot,interval_ones_mask,leading_zero_count,loop_trip_counter,onehot_check,onehot_to_index,permutation_hash,plru_victim_selector,prefix_ones_mask,retry_backoff,sample_majority_filter,secded_decode,secded_encode,secded_layout_pkg,signal_sink,signal_tap,stable_level_filter,trailing_zero_countbus:address_map,address_range_decoder,address_region,address_set_decodercdc:async_gray_queue,async_reqack,cdc_2phase,cdc_2phase_dst,cdc_2phase_src,cdc_2phase_warm_flush,cdc_event_bridge,cdc_event_bridge_ack,cdc_fifo,cdc_fifo_dst,cdc_fifo_src,cdc_fifo_warm_flush,cdc_remote_clear_request,cdc_reset_barrier,cdc_sync,cdc_sync_det,cdc_warm_flush_controller,clearable_async_queue,clearable_two_phase_link,four_phase_mailbox,isochronous_handshake,isochronous_stream_buffer,synchronized_edge,test_reset_synchronizer,two_phase_async_queueclkrst:clk_int_div_simple,clk_int_even_div,clk_int_even_div_static,clk_int_odd_div_static,peak_delta_counter,rs_counter,rs_delta_counter,rst_syncclock:clock_divider,clock_or_tree,safe_clock_muxinterface:ahbl_if,apb4_if,apb4_pure_if,axi4_addr_gen,axi4_if,ram_if,ready_valid_if,ribp_ifmemory:circular_store,memory_bank_adapter,memory_bank_adapter_detail,sync_memory,tag_order_queuemodel:apb4_master_modelstream:bypass_buffer,latest_value_stream,memory_response_bridge,round_robin_arbiter,stream_buffer,stream_collector,stream_credit_limiter,stream_crossbar,stream_delay_injector,stream_discard_gate,stream_elastic_register,stream_fair_arbiter,stream_fallthrough_buffer,stream_queue,stream_replicator,stream_router,stream_selector,stream_shuffle_network,stream_window_guardtech:clk_an2,clk_buf,clk_icg,clk_icg2,clk_mux2,clk_n,clk_nd2,clk_xor2,osc_pad_h,osc_pad_v,tech_pll,tech_ram,tech_ram_bm,tech_regfile,tech_regfile_bm,tri_pd_pad_h,tri_pd_pad_v,tri_pdu_pad_h,tri_pdu_pad_v,tri_pu_pad_h,tri_pu_pad_vutils:bin2gray,dff,dffer,dfferc,dffercn,dfferh,dfferm,dffesr,dffl,dffr,dffrc,dffrh,dffsr,edge_det,edge_det_fe,edge_det_re,edge_det_sync,edge_det_sync_fe,edge_det_sync_re,fifo,gray2bin,lfsr_fibonacci,lfsr_galois,ndffr,regfield,shift_reg,spill_register,stream_fifo,valid_delay_line,xchecker