- Created documentation for , , , and modules, detailing their functionality, parameters, and usage examples.
- Implemented a script to ensure required headings and content are present in documentation files.
- Developed to generate and update documentation pages from SystemVerilog declarations, ensuring consistency and completeness.
- Introduced , , , , , , , and for advanced stream processing capabilities.
- Implemented to manage memory response channels with a response queue.
- Added module for delaying valid-tagged data without a ready path.
- Created script to validate PULP coverage manifest entries and ensure compliance with licensing requirements.
- Introduced formal verification script for stream_window module.
- Added stream_window_formal.sv to define assertions for the stream window logic.
- Implemented SECDED (Single Error Correction Double Error Detection) encoder and decoder in ecc_secded.sv.
- Created a pseudo-LRU victim selector module for cache replacement policy in replacement.sv.
- Developed cdc_warm_flush_controller for coordinated CDC flush operations in cdc_warm_flush.sv.
- Added peak_delta_counter for tracking peak values in counter.sv.
- Introduced ribp_if interface for communication between master and slave components.
- Implemented stream_control module for managing input/output stream operations.
- Updated doctor.sh script to include bitwuzla in the toolchain check.
- Created install_toolchain.py for managing toolchain installations with checksum verification.
- Added geometry validation for BIT_WIDTH, WORD_DEPTH, and ADDR_WIDTH in tech_ram, tech_ram_bm, tech_regfile, and tech_regfile_bm modules to ensure proper configurations.
- Implemented address range checks in tech_ram, tech_ram_bm, tech_regfile, and tech_regfile_bm modules to prevent out-of-bounds access.
- Improved error messages for unsupported access types in regfield module, including validation for DATA_WIDTH.
- Added DATA_WIDTH validation in spill_register module to ensure positive values.
- Refactored APB4AXI4Master and APB4Master classes to streamline constructor definitions and improve readability.
- Enhanced AXI4Master class with additional burst address calculations and legality checks for read/write operations.
- Updated read/write tasks in AXI4Master to include error handling for response mismatches and illegal burst conditions.
- Simplified the filtering of reference data in rd_check task of AXI4Master to improve clarity and maintainability.
- Cleaned up the TestBase class constructor for consistency and clarity.
- Updated license headers to use SPDX format across all RTL files.
- Enhanced error checking in various modules (e.g., tech_ram, tech_regfile, bin2gray, gray2bin, lfsr) to validate parameters and prevent invalid configurations.
- Refactored FIFO implementation to simplify pointer management and ensure proper handling of push/pop operations.
- Introduced new scripts for checking formatting and license headers, ensuring compliance with project standards.
- Added style guidelines to maintain consistent coding practices across the RTL codebase.
- Updated testbench files to include license headers and maintain compatibility with legacy structures.
maksyuki