mirror of
https://github.com/retroSoC/common.git
synced 2026-11-04 22:32:37 +00:00
maksyuki
a542f1ee57
- Added geometry validation for BIT_WIDTH, WORD_DEPTH, and ADDR_WIDTH in tech_ram, tech_ram_bm, tech_regfile, and tech_regfile_bm modules to ensure proper configurations. - Implemented address range checks in tech_ram, tech_ram_bm, tech_regfile, and tech_regfile_bm modules to prevent out-of-bounds access. - Improved error messages for unsupported access types in regfield module, including validation for DATA_WIDTH. - Added DATA_WIDTH validation in spill_register module to ensure positive values. - Refactored APB4AXI4Master and APB4Master classes to streamline constructor definitions and improve readability. - Enhanced AXI4Master class with additional burst address calculations and legality checks for read/write operations. - Updated read/write tasks in AXI4Master to include error handling for response mismatches and illegal burst conditions. - Simplified the filtering of reference data in rd_check task of AXI4Master to improve clarity and maintainability. - Cleaned up the TestBase class constructor for consistency and clarity.
108 lines
2.8 KiB
Systemverilog
108 lines
2.8 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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// Small combinational primitives intentionally have no external dependency.
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module bit_count #(
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parameter int WIDTH = 32,
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parameter int COUNT_WIDTH = $clog2(WIDTH + 1)
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) (
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input logic [ WIDTH-1:0] value_i,
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output logic [COUNT_WIDTH-1:0] count_o
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);
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initial begin
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if (WIDTH < 1 || COUNT_WIDTH < $clog2(WIDTH + 1)) begin
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$fatal(1, "bit_count: WIDTH must be positive and COUNT_WIDTH sufficient");
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end
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end
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always_comb begin
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count_o = '0;
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for (int unsigned bit_idx = 0; bit_idx < WIDTH; bit_idx++) begin
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count_o = count_o + value_i[bit_idx];
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end
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end
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endmodule
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module leading_zero_count #(
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parameter int WIDTH = 32,
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parameter int COUNT_WIDTH = $clog2(WIDTH + 1)
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) (
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input logic [ WIDTH-1:0] value_i,
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output logic [COUNT_WIDTH-1:0] count_o,
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output logic all_zero_o
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);
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logic s_seen_one;
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initial begin
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if (WIDTH < 1 || COUNT_WIDTH < $clog2(WIDTH + 1)) begin
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$fatal(1, "leading_zero_count: WIDTH must be positive and COUNT_WIDTH sufficient");
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end
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end
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always_comb begin
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count_o = '0;
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s_seen_one = 1'b0;
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for (int bit_idx = WIDTH - 1; bit_idx >= 0; bit_idx--) begin
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if (!s_seen_one && value_i[bit_idx]) begin
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s_seen_one = 1'b1;
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end else if (!s_seen_one) begin
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count_o = count_o + 1'b1;
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end
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end
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all_zero_o = !s_seen_one;
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end
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endmodule
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module onehot_check #(
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parameter int WIDTH = 32,
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parameter bit ALLOW_ZERO = 1'b0
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) (
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input logic [WIDTH-1:0] value_i,
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output logic valid_o
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);
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initial begin
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if (WIDTH < 1) $fatal(1, "onehot_check: WIDTH must be positive");
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end
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always_comb begin
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valid_o = (value_i != '0) && ((value_i & (value_i - 1'b1)) == '0);
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if (ALLOW_ZERO && value_i == '0) begin
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valid_o = 1'b1;
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end
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end
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endmodule
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module onehot_to_index #(
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parameter int WIDTH = 32,
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parameter int INDEX_WIDTH = (WIDTH > 1) ? $clog2(WIDTH) : 1
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) (
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input logic [ WIDTH-1:0] value_i,
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output logic [INDEX_WIDTH-1:0] index_o,
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output logic valid_o
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);
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logic [WIDTH-1:0] s_onehot;
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initial begin
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if (WIDTH < 1 || INDEX_WIDTH < ((WIDTH > 1) ? $clog2(WIDTH) : 1)) begin
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$fatal(1, "onehot_to_index: WIDTH must be positive and INDEX_WIDTH sufficient");
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end
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end
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onehot_check #(
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.WIDTH (WIDTH),
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.ALLOW_ZERO(1'b0)
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) u_onehot_check (
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.value_i(value_i),
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.valid_o(valid_o)
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);
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assign s_onehot = value_i;
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always_comb begin
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index_o = '0;
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for (int unsigned bit_idx = 0; bit_idx < WIDTH; bit_idx++) begin
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if (s_onehot[bit_idx]) begin
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index_o = INDEX_WIDTH'(bit_idx);
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end
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end
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end
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endmodule
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