mirror of
https://github.com/retroSoC/common.git
synced 2026-11-04 22:32:37 +00:00
maksyuki
cbbc335159
- Introduced , , , , , , , and for advanced stream processing capabilities. - Implemented to manage memory response channels with a response queue. - Added module for delaying valid-tagged data without a ready path. - Created script to validate PULP coverage manifest entries and ensure compliance with licensing requirements.
44 lines
1.4 KiB
Systemverilog
44 lines
1.4 KiB
Systemverilog
// Copyright 2020 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy at
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// http://solderpad.org/licenses/SHL-0.51.
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// SPDX-License-Identifier: SHL-0.51
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//
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// Derived design work: Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// Design independently implemented for common; see NOTICE for attribution.
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// Reduces a set of already-safe gated clocks. Callers must ensure inputs do
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// not overlap high; this is a clock construction primitive, not a mux.
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module clock_or_tree #(
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parameter int CLOCKS = 2
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) (
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input logic [CLOCKS-1:0] clock_i,
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output logic clock_o
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);
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if (CLOCKS == 1) begin : GEN_LEAF
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assign clock_o = clock_i[0];
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end else begin : GEN_TREE
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localparam int LEFT_CLOCKS = CLOCKS / 2;
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localparam int RIGHT_CLOCKS = CLOCKS - LEFT_CLOCKS;
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logic s_left;
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logic s_right;
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clock_or_tree #(
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.CLOCKS(LEFT_CLOCKS)
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) u_left (
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.clock_i(clock_i[0+:LEFT_CLOCKS]),
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.clock_o(s_left)
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);
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clock_or_tree #(
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.CLOCKS(RIGHT_CLOCKS)
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) u_right (
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.clock_i(clock_i[LEFT_CLOCKS+:RIGHT_CLOCKS]),
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.clock_o(s_right)
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);
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assign clock_o = s_left | s_right;
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end
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initial begin
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if (CLOCKS < 1) $fatal(1, "clock_or_tree: CLOCKS must be positive");
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end
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endmodule
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