mirror of
https://github.com/retroSoC/common.git
synced 2026-11-04 22:32:37 +00:00
maksyuki
a542f1ee57
- Added geometry validation for BIT_WIDTH, WORD_DEPTH, and ADDR_WIDTH in tech_ram, tech_ram_bm, tech_regfile, and tech_regfile_bm modules to ensure proper configurations. - Implemented address range checks in tech_ram, tech_ram_bm, tech_regfile, and tech_regfile_bm modules to prevent out-of-bounds access. - Improved error messages for unsupported access types in regfield module, including validation for DATA_WIDTH. - Added DATA_WIDTH validation in spill_register module to ensure positive values. - Refactored APB4AXI4Master and APB4Master classes to streamline constructor definitions and improve readability. - Enhanced AXI4Master class with additional burst address calculations and legality checks for read/write operations. - Updated read/write tasks in AXI4Master to include error handling for response mismatches and illegal burst conditions. - Simplified the filtering of reference data in rd_check task of AXI4Master to improve clarity and maintainability. - Cleaned up the TestBase class constructor for consistency and clarity.
263 lines
9.1 KiB
Systemverilog
263 lines
9.1 KiB
Systemverilog
// Copyright 2018-2024 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51. You may obtain a copy at
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// http://solderpad.org/licenses/SHL-0.51.
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//
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// Derived design work: Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: SHL-0.51
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// Design independently implemented for common; see NOTICE for attribution.
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module bypass_buffer #(
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parameter int DATA_WIDTH = 32
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) (
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input logic flush_i,
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input logic in_valid_i,
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output logic in_ready_o,
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input logic [DATA_WIDTH-1:0] in_data_i,
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output logic out_valid_o,
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input logic out_ready_i,
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output logic [DATA_WIDTH-1:0] out_data_o
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);
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initial begin
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if (DATA_WIDTH < 1) $fatal(1, "bypass_buffer: DATA_WIDTH must be positive");
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end
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assign in_ready_o = out_ready_i && !flush_i;
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assign out_valid_o = in_valid_i && !flush_i;
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assign out_data_o = in_data_i;
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endmodule
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// Reuses the two-entry registered common primitive for elastic timing relief.
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module stream_buffer #(
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parameter int DATA_WIDTH = 32,
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parameter bit TRANSPARENT = 1'b0
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) (
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input logic clk_i,
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input logic rst_n_i,
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input logic flush_i,
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input logic in_valid_i,
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output logic in_ready_o,
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input logic [DATA_WIDTH-1:0] in_data_i,
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output logic out_valid_o,
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input logic out_ready_i,
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output logic [DATA_WIDTH-1:0] out_data_o
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);
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initial begin
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if (DATA_WIDTH < 1) $fatal(1, "stream_buffer: DATA_WIDTH must be positive");
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end
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spill_register #(
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.DATA_WIDTH(DATA_WIDTH),
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.BYPASS (TRANSPARENT)
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) u_spill_register (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.flush_i(flush_i),
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.valid_i(in_valid_i),
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.ready_o(in_ready_o),
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.data_i (in_data_i),
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.valid_o(out_valid_o),
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.ready_i(out_ready_i),
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.data_o (out_data_o)
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);
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endmodule
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module stream_selector #(
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parameter int DATA_WIDTH = 32,
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parameter int PORTS = 4,
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parameter int SELECT_WIDTH = (PORTS > 1) ? $clog2(PORTS) : 1
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) (
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input logic [SELECT_WIDTH-1:0] select_i,
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input logic [ PORTS-1:0] in_valid_i,
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output logic [ PORTS-1:0] in_ready_o,
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input logic [ PORTS-1:0][DATA_WIDTH-1:0] in_data_i,
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output logic out_valid_o,
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input logic out_ready_i,
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output logic [ DATA_WIDTH-1:0] out_data_o
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);
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initial begin
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if (DATA_WIDTH < 1 || PORTS < 1 || SELECT_WIDTH < ((PORTS > 1) ? $clog2(PORTS) : 1)) begin
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$fatal(1, "stream_selector: invalid data, port, or select width");
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end
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end
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always_comb begin
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in_ready_o = '0;
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out_valid_o = 1'b0;
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out_data_o = '0;
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// The comparison is only non-trivial for a non-power-of-two port count.
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// verilator lint_off CMPCONST
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if (select_i <= SELECT_WIDTH'(PORTS - 1)) begin
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// verilator lint_on CMPCONST
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out_valid_o = in_valid_i[select_i];
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out_data_o = in_data_i[select_i];
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in_ready_o[select_i] = out_ready_i;
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end
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end
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endmodule
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module stream_router #(
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parameter int DATA_WIDTH = 32,
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parameter int PORTS = 4,
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parameter int SELECT_WIDTH = (PORTS > 1) ? $clog2(PORTS) : 1
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) (
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input logic [SELECT_WIDTH-1:0] select_i,
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input logic in_valid_i,
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output logic in_ready_o,
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input logic [ DATA_WIDTH-1:0] in_data_i,
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output logic [ PORTS-1:0] out_valid_o,
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input logic [ PORTS-1:0] out_ready_i,
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output logic [ PORTS-1:0][DATA_WIDTH-1:0] out_data_o
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);
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initial begin
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if (DATA_WIDTH < 1 || PORTS < 1 || SELECT_WIDTH < ((PORTS > 1) ? $clog2(PORTS) : 1)) begin
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$fatal(1, "stream_router: invalid data, port, or select width");
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end
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end
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always_comb begin
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in_ready_o = 1'b0;
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out_valid_o = '0;
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out_data_o = '0;
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// The comparison is only non-trivial for a non-power-of-two port count.
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// verilator lint_off CMPCONST
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if (select_i <= SELECT_WIDTH'(PORTS - 1)) begin
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// verilator lint_on CMPCONST
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in_ready_o = out_ready_i[select_i];
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out_valid_o[select_i] = in_valid_i;
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out_data_o[select_i] = in_data_i;
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end
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end
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endmodule
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module stream_replicator #(
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parameter int DATA_WIDTH = 32,
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parameter int PORTS = 4
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) (
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input logic clk_i,
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input logic rst_n_i,
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input logic flush_i,
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input logic in_valid_i,
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output logic in_ready_o,
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input logic [DATA_WIDTH-1:0] in_data_i,
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input logic [ PORTS-1:0] enable_i,
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output logic [ PORTS-1:0] out_valid_o,
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input logic [ PORTS-1:0] out_ready_i,
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output logic [ PORTS-1:0][DATA_WIDTH-1:0] out_data_o
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);
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logic [DATA_WIDTH-1:0] r_payload;
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logic [ PORTS-1:0] r_pending;
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logic r_active;
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logic [ PORTS-1:0] s_pending_after_transfer;
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initial begin
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if (DATA_WIDTH < 1 || PORTS < 1) begin
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$fatal(1, "stream_replicator: DATA_WIDTH and PORTS must be positive");
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end
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end
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// The target mask and payload are sampled on the input handshake. Every
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// enabled target keeps valid asserted until its own transfer completes.
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assign in_ready_o = !r_active && !flush_i;
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assign out_valid_o = r_pending & {PORTS{r_active && !flush_i}};
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assign s_pending_after_transfer = r_pending & ~out_ready_i;
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for (genvar port_idx = 0; port_idx < PORTS; port_idx++) begin : GEN_REPLICA_DATA
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assign out_data_o[port_idx] = r_payload;
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end
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always_ff @(posedge clk_i or negedge rst_n_i) begin
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if (!rst_n_i) begin
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r_payload <= '0;
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r_pending <= '0;
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r_active <= 1'b0;
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end else if (flush_i) begin
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r_pending <= '0;
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r_active <= 1'b0;
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end else if (!r_active) begin
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if (in_valid_i) begin
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r_payload <= in_data_i;
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r_pending <= enable_i;
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r_active <= |enable_i;
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end
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end else begin
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r_pending <= s_pending_after_transfer;
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if (s_pending_after_transfer == '0) begin
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r_active <= 1'b0;
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end
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end
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end
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endmodule
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module stream_collector #(
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parameter int DATA_WIDTH = 32,
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parameter int PORTS = 4
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) (
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input logic [ PORTS-1:0] in_valid_i,
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output logic [ PORTS-1:0] in_ready_o,
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input logic [ PORTS-1:0][DATA_WIDTH-1:0] in_data_i,
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input logic [ PORTS-1:0] enable_i,
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output logic out_valid_o,
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input logic out_ready_i,
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output logic [PORTS*DATA_WIDTH-1:0] out_data_o
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);
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logic s_all_present;
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initial begin
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if (DATA_WIDTH < 1 || PORTS < 1) begin
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$fatal(1, "stream_collector: DATA_WIDTH and PORTS must be positive");
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end
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end
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assign s_all_present = |enable_i && &(in_valid_i | ~enable_i);
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assign out_valid_o = s_all_present;
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assign in_ready_o = {PORTS{out_ready_i && s_all_present}} & enable_i;
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assign out_data_o = in_data_i;
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endmodule
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module stream_credit_limiter #(
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parameter int DATA_WIDTH = 32,
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parameter int MAX_CREDITS = 4,
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parameter int CREDIT_WIDTH = $clog2(MAX_CREDITS + 1)
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) (
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input logic clk_i,
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input logic rst_n_i,
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input logic flush_i,
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input logic release_i,
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input logic in_valid_i,
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output logic in_ready_o,
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input logic [ DATA_WIDTH-1:0] in_data_i,
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output logic out_valid_o,
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input logic out_ready_i,
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output logic [ DATA_WIDTH-1:0] out_data_o,
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output logic [CREDIT_WIDTH-1:0] credit_o
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);
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logic [CREDIT_WIDTH-1:0] r_credit;
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logic s_accept;
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initial begin
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if (DATA_WIDTH < 1 || MAX_CREDITS < 1 || CREDIT_WIDTH < $clog2(MAX_CREDITS + 1)) begin
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$fatal(1, "stream_credit_limiter: invalid data, credit, or counter width");
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end
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end
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assign out_valid_o = in_valid_i && (r_credit != '0) && !flush_i;
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assign in_ready_o = out_ready_i && (r_credit != '0) && !flush_i;
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assign out_data_o = in_data_i;
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assign s_accept = out_valid_o && out_ready_i;
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assign credit_o = r_credit;
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always_ff @(posedge clk_i or negedge rst_n_i) begin
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if (!rst_n_i || flush_i) begin
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r_credit <= CREDIT_WIDTH'(MAX_CREDITS);
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end else begin
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case ({
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release_i && (r_credit < CREDIT_WIDTH'(MAX_CREDITS)), s_accept
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})
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2'b10: r_credit <= r_credit + 1'b1;
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2'b01: r_credit <= r_credit - 1'b1;
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default: r_credit <= r_credit;
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endcase
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end
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end
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endmodule
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